QL3060

High Performance & High Density
` Densities up to 60,000 usable PLD gates with 316 I/Os
` Fastest FPGA family available at any density level
` 16-bit counter speeds over 300 MHz, data path speeds over 400 MH
Easy to Use / Fast Development Cycles
` Abundant interconnect makes devices 100% routable with pin-outs locked
` Variable-grain logic cell provides high performance and 100% logic utilization
` Comprehensive design tools include fast, efficient Verilog/VHDL synthesis
Low Cost
` 0.35m four-layer metal non-volatile CMOS process
` Small die sizes - first FPGA family to use staggered pads
Advanced I/O Capabilities
` Multi-volt compatible I/Os for 3.3 volt and 5 volt system interfaces
` PCI compatibility with 3.3V and 5.0V buses
` Full JTAG boundary scan
` Registered I/O cells with individually controlled clocks and output enables

The QL3060 is fabricated on a 0.35mm 4- layer metal process using QuickLogic's patented ViaLink" technology to provide a unique combination of high performance, high density, low cost, and complete flexibility. The QL3060 in the family range from 4,000 usable PLD gates with 82 I/Os to 60,000 usable PLD gates with 3163 I/Os, making them among the largest FPGAs available. While other FPGA families sacrifice performance to reach these densities, the QL3060 is the fastest available from any vendor at any density level - with 16-bit counter speeds that exceed 300 MHz and datapath speeds over 400 MHz.

With die sizes as small as half those of competing FPGAs, QL3060 provide high levels of density and performance at a lower cost. The QL3060 also provides 100% routability, even with all logic cells used and I/O pins fixed. This capability is critical for larger designs completed using high-level hardware description languages such as Verilog and VHDL.

QL3060 in the pASIC 3 family are based on an array of highly flexible logic cells which have been optimized to efficiently implement a wide range of logic functions at high speed. Each cell can implement one large function, five independent smaller functions, or any combination in-between.

Logic cells are configured and interconnected by
rows and columns of routing metal and ViaLink metal-to-metal antifuses. Because ViaLink antifuses are small, fast, and are placed between metal layers above the logic cells (rather than on the silicon substrate), QL3060 can be located at every routing track junction. This approach allows abundant interconnect resources with small die sizes.

QL3060 feature 3.3 volt operation with multi-volt compatible I/Os. Thus the devices can easily operate in 3 volt only systems, as well as mixed 3.3 volt/5 volt systems.

A wide range of additional family features complements the pASIC 3 family. All members include 5 volt and 3 volt PCI-compliant speed grades capable of implementing bus master and target applications at 33 MHz with zero wait states. I/O pins provide  individually-controlled output enables, dedicated input/feedback registers, and full JTAG capability for boundary scan and test. Different family members in the same package are pin-compatible with one another, permitting easy design migration within the family. In addition, QL3060 provide the benefits of non-volatility, high design security, immediate functionality on power-up, and self-contained single chip solutions.