PKD01, PKD01AY/883, PKD01AY/883A Selling Leads, Datasheet
MFG:AD Package Cooled:DIP D/C:0725+
PKD01, PKD01AY/883, PKD01AY/883A Datasheet download
Part Number: PKD01
MFG: AD
Package Cooled: DIP
D/C: 0725+
PKD01, PKD01AY/883, PKD01AY/883A
- Table of contents:
Info of PKD01
Info of PKD01AY/883
Info of PKD01AY/883A
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About PKD01
PDF/DataSheet Download
Datasheet: PKD01
File Size: 412601 KB
Manufacturer: AD [Analog Devices]
Download : Click here to Download
About PKD01AY/883
PDF/DataSheet Download
Datasheet: PKD01AY/883
File Size: 412664 KB
Manufacturer:
Download : Click here to Download
About PKD01
PDF/DataSheet Download
Datasheet: PKD01
File Size: 412601 KB
Manufacturer: AD [Analog Devices]
Download : Click here to Download
PKD01 General Description
The PKD01 tracks an analog input signal until a maximum amplitude is reached. The maximum value is then retained as a peak voltage on a hold capacitor. Being a monolithic circuit, the PKD01 offers significant performance and package density advantages over hybrid modules and discrete designs without sacrificing system versatility. The matching characteristics attained in a monolithic circuit provide inherent advantages when charge injection and droop rate error reduction are primary goals.
Innovative design techniques maximize the advantages of monolithic technology. Transconductance (gm) amplifiers were chosen over conventional voltage amplifier circuit building blocks. The gm amplifiers simplify internal frequency compensation, minimize acquisition time and maximize circuit accuracy. Their outputs are easily switched by low glitch current steering circuits. The steered outputs are clamped to reduce charge injection errors upon entering the hold mode or exiting the reset mode. The inherently low zero-scale error is further reduced by active Zener-Zap trimming to optimize overall accuracy.
The output buffer amplifier features an FET input stage to reduce droop rate error during lengthy peak hold periods. A bias current cancellation circuit minimizes droop error at high ambient temperatures.
Through the DET control pin, new peaks may either be detected or ignored. Detected peaks are presented as positive output levels. Positive or negative peaks may be detected without additional active circuits, since Amplifier A can operate as an inverting or noninverting gain stage.
An uncommitted comparator provides many application options.
Status indication and logic shaping/shifting are typical examples.
PKD01 Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Logic and Logic Ground
Voltage . . . . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Amplifier A or B Differential Input Voltage . . . . . . . . . . ±24 V
Comparator Differential Input Voltage . . . . . . . . . . . . . ±24 V
Comparator Output Voltage
. . . . . . . . . . . . . . . . . . . . . . Equal to Positive Supply Voltage
Hold Capacitor Short-Circuit Duration . . . . . . . . . . Indefinite
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
Storage Temperature Range
PKD01AY, PKD01EY, PKD01FY . . . . . 65°C to +150°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . 65°C to +125°C
Operating Temperature Range
PKD01AY . . . . . . . . . . . . . . . . . . . . . . . . 55°C to +125°C
PKD01EY, PKD01FY . . . . . . . . . . . . . . . . 25°C to +85°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature . . . . . . . . . . . . . . . . . 65°C to +150°C
NOTES:
1Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted.
2Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Input Voltage . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Logic and Logic Ground
Voltage . . . . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Amplifier A or B Differential Input Voltage . . . . . . . . . . ±24 V
Comparator Differential Input Voltage . . . . . . . . . . . . . ±24 V
Comparator Output Voltage
. . . . . . . . . . . . . . . . . . . . . . Equal to Positive Supply Voltage
Hold Capacitor Short-Circuit Duration . . . . . . . . . . Indefinite
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
Storage Temperature Range
PKD01AY, PKD01EY, PKD01FY . . . . . 65°C to +150°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . 65°C to +125°C
Operating Temperature Range
PKD01AY . . . . . . . . . . . . . . . . . . . . . . . . 55°C to +125°C
PKD01EY, PKD01FY . . . . . . . . . . . . . . . . 25°C to +85°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature . . . . . . . . . . . . . . . . . 65°C to +150°C
NOTES:
1Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted.
2Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PKD01 Features
·Monolithic Design for Reliability and Low Cost
·High Slew Rate: 0.5 V/s
·Low Droop Rate TA = 25C: 0.1 mV/ms TA = 125C: 10 mV/ms
·Low Zero-Scale Error: 4 mV
·Digitally Selected Hold and Reset Modes
·Reset to Positive or Negative Voltage Levels
·Logic Signals TTL and CMOS Compatible
·Uncommitted Comparator On-Chip
·Available in Die Form
·High Slew Rate: 0.5 V/s
·Low Droop Rate TA = 25C: 0.1 mV/ms TA = 125C: 10 mV/ms
·Low Zero-Scale Error: 4 mV
·Digitally Selected Hold and Reset Modes
·Reset to Positive or Negative Voltage Levels
·Logic Signals TTL and CMOS Compatible
·Uncommitted Comparator On-Chip
·Available in Die Form
PKD01 Connection Diagram
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