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M5M4V64S20ATP, M5M4V64S20ATP-8, M5M4V64S30ATP

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Info of M5M4V64S20ATP
Info of M5M4V64S20ATP-8
Info of M5M4V64S30ATP

M5M4V64S20ATP, M5M4V64S20ATP-8, M5M4V64S30ATP Selling Leads, Datasheet

MFG:MITSUBISHI Package Cooled:TSOP D/C:08+

M5M4V64S20ATP, M5M4V64S20ATP-8, M5M4V64S30ATP Picture

M5M4V64S20ATP, M5M4V64S20ATP-8, M5M4V64S30ATP Datasheet download

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Part Number: M5M4V64S20ATP

MFG: MITSUBISHI

Package Cooled: TSOP

D/C: 08+

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M5M4V64S20ATP-8 General Description

The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S20ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.

M5M4V64S20ATP-8 Maximum Ratings

Symbol	Parameter	Conditions	Ratings	Unit
Vdd	Supply Voltage	with respect to Vss	-0.5 ~ 4.6	V
VddQ	Supply Voltage for Output	with respect to VssQ	-0.5 ~ 4.6	V
VI	Input Voltage	with respect to Vss	-0.5 ~ Vdd+0.5	V
VO	Output Voltage	with respect to VssQ	-0.5 ~ VddQ+0.5	V
IO	Output Current		50	mA
Pd	Power Dissipation	Ta = 25 °C	1000	mW
Topr	Operating Temperature		0 ~ 70	°C
Tstg	Storage Temperature		-65 ~ 150	°C

M5M4V64S20ATP-8 Features

- Single 3.3v±0.3v power supply
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A9
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
- Clock frequency 125MHz / 100MHz / 83MHz

M5M4V64S20ATP-8 Connection Diagram

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