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M48Z12-70PCI, M48Z128, M48Z128-100

Table of contents:
Info of M48Z12-70PCI
Info of M48Z128
Info of M48Z128-100

M48Z12-70PCI, M48Z128, M48Z128-100 Selling Leads, Datasheet

MFG:STM Package Cooled:STM D/C:04+

M48Z12-70PCI, M48Z128, M48Z128-100 Picture

M48Z12-70PCI, M48Z128, M48Z128-100 Datasheet download

Five Points

Part Number: M48Z12-70PCI

MFG: STM

Package Cooled: STM

D/C: 04+

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M48Z128 General Description

The M48Z128/128Y ZEROPOWER^®RAM is a 128 Kbit x8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution.

The M48Z128/128Y is a non-volatile pin and function equivalent to any JEDEC standard 128K x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 32 pin 600mil DIP Module houses the M48Z128/128Y silicon with a long life lithium button cell in a single package.

For surface mount environments ST provides a Chip Set solution consisting of a 28 pin 330mil SOIC NVRAM Supervisor (M40Z300) and a 32 pin TSOP (8 x 20mm) LPSRAM (M68Z128) packages.

The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery.

M48Z128 Maximum Ratings

Symbol	Parameter	Value	Unit
T_A	Ambient Operating Temperature	0 to 70
T_STG	Storage Temperature (V_CC Off)	40 to 70
T_BIAS	Temperature Under Bias	10 to 70
T_SLD⁽²⁾	Lead Solder Temperature for 10 seconds	260
V_IO	Input or Output Voltages	0.3 to 7	V
V_CC	Supply Voltage	0.3 to 7	V

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
              permanent damage to the device. This is a stress rating only and functional operation
             of the device at these or any other conditions above those indicated in the operational
             section of this specification is not implied. Exposure to the absolute maximum rating conditions
             for extended periods of time may affect reliability.
        2. Soldering temperature not to exceed 260 for 10 seconds (total thermal budget not to exceed
            150 for longer than 30 seconds).

CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.

M48Z128 Features

` INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY
` CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES
` 10 YEARS of DATA RETENTION in the ABSENCE of POWER
` AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION
` WRITE PROTECT VOLTAGES (V_PFD = Power-fail Deselect Voltage):
   M48Z128: 4.50V 3 V_PFD 3 4.75V
   M48Z128Y: 4.20V 3 V_PFD 3 4.50V
` BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED
` PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 128K x 8 SRAMs
` SURFACE MOUNT CHIP SET PACKAGING INCLUDES a 28-PIN SOIC and a 32-LEAD TSOP (SNAPHAT TOP TO
    BE ORDERED SEPARATELY)
` SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP WHICH CONTAINS the BATTERY
` SNAPHAT^®HOUSING (BATTERY) IS REPLACEABLE

M48Z128 Connection Diagram

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