LU3X31T2-T64, LU3X31T-T64, LU3X31T-T64-DB Selling Leads, Datasheet
MFG:AGERE Package Cooled:QFP-64 D/C:03+
LU3X31T2-T64, LU3X31T-T64, LU3X31T-T64-DB Datasheet download
Part Number: LU3X31T2-T64
MFG: AGERE
Package Cooled: QFP-64
D/C: 03+
LU3X31T2-T64, LU3X31T-T64, LU3X31T-T64-DB
- Table of contents:
Info of LU3X31T2-T64
Info of LU3X31T-T64
Info of LU3X31T-T64-DB
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About LU3X31T-T64
PDF/DataSheet Download
Datasheet: LU3X31T-T64
File Size: 594188 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
About LU3X31T-T64
PDF/DataSheet Download
Datasheet: LU3X31T-T64
File Size: 594188 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
About LU3X31T-T64
PDF/DataSheet Download
Datasheet: LU3X31T-T64
File Size: 594188 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
LU3X31T-T64 General Description
MII Isolate Mode. The LU3X31T-T64 implements an MII isolate mode that is controlled by bit 10 of the control
register (register 0h). The LU3X31T-T64 will set this bit to one if the PHY address is set to 00000 upon powerup/
hardware reset. Otherwise, the LU3X31T-T64 will initialize this bit to 0. Setting this bit to a 1 will put the
LU3X31T-T64 into isolate mode. The isolate mode can also be activated by setting the PHY address (bits 15 through 11 of register 19h) to 0 through the serial management interface, although the content of the isolate register is not affected by the modification of PHY address. The LU3X31T-T64 does not respond to packet data present at TXD[3:0], TXEN, and TXER inputs and presents a high impedance on the TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS outputs. The LU3X31T-T64 will continue to respond to all management transactions.
register (register 0h). The LU3X31T-T64 will set this bit to one if the PHY address is set to 00000 upon powerup/
hardware reset. Otherwise, the LU3X31T-T64 will initialize this bit to 0. Setting this bit to a 1 will put the
LU3X31T-T64 into isolate mode. The isolate mode can also be activated by setting the PHY address (bits 15 through 11 of register 19h) to 0 through the serial management interface, although the content of the isolate register is not affected by the modification of PHY address. The LU3X31T-T64 does not respond to packet data present at TXD[3:0], TXEN, and TXER inputs and presents a high impedance on the TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS outputs. The LU3X31T-T64 will continue to respond to all management transactions.
LU3X31T-T64 Features
Single-chip integrated physical layer and transceiver for 10Base-T and/or 100Base-T functions
IEEE 802.3 compatible 10Base-T and 100Base-T physical layer interface and ANSI X3.263 TP-PMD compatible transceiver
Built-in analog 10 Mbits/s receive filter, eliminating the need for external filters
Built-in 10 Mbits/s transmit filter
10 Mbits/s PLL exceeding tolerances for both preamble and data jitter
100 Mbits/s PLL, combined with the digital adaptive equalizer, robustly handles variations in risefall time, excessive attenuation due to channel loss, duty-cycle distortion, crosstalk, and baseline wander
Transmit rise-fall time can be manipulated to provid ower emissions, amplitude fully compatible for proper interoperability
Programmable scrambler seed for better FCC compliancy
IEEE 802.3u Clause 28 compliant autonegotiation for full 10 Mbits/s and 100 Mbits/s control
Fully configurable via pins and management accesses
Extended management support with interrupt capabilities
PHY MIB support
Symbol mode option
Low-power operation: <150 mA max
Low autonegotiation power: <30 mA
Very low powerdown mode: <5 mA
64-pin TQFP package (10 mm x 10 mm x 1.4 mm)100 Mbits/s PLL, combined with the digital adaptive equalizer, robustly handles variations in risefall time, excessive attenuation due to channel loss, duty-cycle distortion, crosstalk, and baseline wander
Transmit rise-fall time can be manipulated to provide lower emissions, amplitude fully compatible for proper interoperability
Programmable scrambler seed for better FCC compliancy
IEEE 802.3u Clause 28 compliant autonegotiation for full 10 Mbits/s and 100 Mbits/s control
Fully configurable via pins and management accesses
Extended management support with interrupt capabilities
PHY MIB support
Symbol mode option
Low-power operation: <150 mA max
Low autonegotiation power: <30 mA
Very low powerdown mode: <5 mA
64-pin TQFP package (10 mm x 10 mm x 1.4 mm)
LU3X31T-T64 Connection Diagram
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