LC895127-PA4, LC89512W, LC89512W-V25 Selling Leads, Datasheet
MFG:1799 Package Cooled:QFP D/C:01+
LC895127-PA4, LC89512W, LC89512W-V25 Datasheet download
Part Number: LC895127-PA4
MFG: 1799
Package Cooled: QFP
D/C: 01+
LC895127-PA4, LC89512W, LC89512W-V25
- Table of contents:
Info of LC895127-PA4
Info of LC89512W
Info of LC89512W-V25
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About LC8.0
PDF/DataSheet Download
Datasheet: LC8.0
File Size: 600987 KB
Manufacturer: MICROSEMI [Microsemi Corporation]
Download : Click here to Download
About LC89512W
PDF/DataSheet Download
Datasheet: LC89512W
File Size: 53908 KB
Manufacturer: SANYO [Sanyo Semicon Device]
Download : Click here to Download
About LC8.0
PDF/DataSheet Download
Datasheet: LC8.0
File Size: 600987 KB
Manufacturer: MICROSEMI [Microsemi Corporation]
Download : Click here to Download
LC89512W General Description
The LC89512W integrates a real-time error correction circuit and a SCSI interface in a single chip.
LC89512W Maximum Ratings
| Parameter | Symbol | Conditions | Ratings | Unit |
| Maximum power supply voltage | VDD max | Ta = 25 | 0.3 to +7.0 | V |
| I/O voltage | VI, VO | Ta = 25 | 0.3 to VDD+0.3 | V |
| Allowable power dissipation | Pd max | Ta 70 | 350 | mW |
| Operating temperature | Topr | 30 to +70 | ||
| Storage temperature | Tstg | 55 to +125 | ||
| Solder resistance (Pins only) | 10 seconds | 260 |
LC89512W Features
• Support for double-speed drives at an operating frequency of 16.9344 MHz Either SRAM (120 ns), DRAM (80 ns) or pseudo SRAM (85 ns) can be used.
• Support for quad-speed drives at an operating frequency of 33.8688 MHz SRAM (70 ns) must be used.
• Built-in SCSI interface with built-in 48 mA sink buffer (Only the TARGET function is supported.)
• Built-in 12-byte output FIFO for sub-CPU to host computer data transmission
• Built-in 12-byte input FIFO for host computer to sub-CPU data transmission
• Subcode data can be written to buffer RAM and the sub-CPU can read the subcode values by connecting the LC89512 to the CD-DSP subcode pin.
• Sub-CPU access of buffer RAM through the LC89512
• Built-in function for buffer RAM internal data transfer
• Pseudo-SRAM (128-kword ×8-bit and smaller) can be used.
• DRAM (two 256-kword ×4-bit chips or two 1-Mword×4-bit chips) can be used.
• Transfer speeds:
2.8 MB/second (asynchronous mode) (for CD-ROM decode only operation)
4.2 MB/second (synchronous mode) (CD-ROM decode
operation is not supported in synchronous mode)
Both of these transfer modes use a 16.9344 MHz clock.
(The transfer speed depends on the frequency used.)
• Operating frequencies: 16.9344 MHz (up to double speed), 33.8688 (quad speed)
• Support for quad-speed drives at an operating frequency of 33.8688 MHz SRAM (70 ns) must be used.
• Built-in SCSI interface with built-in 48 mA sink buffer (Only the TARGET function is supported.)
• Built-in 12-byte output FIFO for sub-CPU to host computer data transmission
• Built-in 12-byte input FIFO for host computer to sub-CPU data transmission
• Subcode data can be written to buffer RAM and the sub-CPU can read the subcode values by connecting the LC89512 to the CD-DSP subcode pin.
• Sub-CPU access of buffer RAM through the LC89512
• Built-in function for buffer RAM internal data transfer
• Pseudo-SRAM (128-kword ×8-bit and smaller) can be used.
• DRAM (two 256-kword ×4-bit chips or two 1-Mword×4-bit chips) can be used.
• Transfer speeds:
2.8 MB/second (asynchronous mode) (for CD-ROM decode only operation)
4.2 MB/second (synchronous mode) (CD-ROM decode
operation is not supported in synchronous mode)
Both of these transfer modes use a 16.9344 MHz clock.
(The transfer speed depends on the frequency used.)
• Operating frequencies: 16.9344 MHz (up to double speed), 33.8688 (quad speed)
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