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K9LAG08, K9LAG08U0M, K9LAG08U0M-PCB

Table of contents:
Info of K9LAG08
Info of K9LAG08U0M
Info of K9LAG08U0M-PCB

K9LAG08, K9LAG08U0M, K9LAG08U0M-PCB Selling Leads, Datasheet

MFG:12000 Package Cooled:SAMSUNG D/C:07+

K9LAG08, K9LAG08U0M, K9LAG08U0M-PCB Picture

K9LAG08, K9LAG08U0M, K9LAG08U0M-PCB Datasheet download

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Part Number: K9LAG08

MFG: 12000

Package Cooled: SAMSUNG

D/C: 07+

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K9LAG08U0M General Description

Offered in 2Gx8bit, the K9LAG08U0M is a 16G-bit NAND Flash Memory with spare 512M-bit. Its NAND cell provides the most costeffective solution for the solid state mass storage market. A program operation can be performed in typical 800µs on the 2,112-byte page and an erase operation can be performed in typical 1.5ms on a (256K+8K)byte block. Data in the data register can be read out at 30ns(K9MCG08U5M:50ns) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9LAG08U0Ms extended reliability of 5K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9LAG08U0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

An ultra high density solution having two 16Gb stacked with two chip selects is also available in standard TSOPI package.

K9LAG08U0M Maximum Ratings

Parameter		Symbol	Rating	Notes
Voltage on any pin relative to V_SS		V_CC	-0.6 to + 4.6	V
		V_IN	-0.6 to + 4.6
		V_I/O	-0.6 to Vcc+0.3 (<4.6V)
Temperature Under Bias	K9XXG08UXM XCB0	T_BIAS	-10 to +125
	K9XXG08UXM-XIB0		-40 to +125
Storage Temperature	K9XXG08UXM XCB0	T_STG	-65 to +150
	K9XXG08UXM-XIB0
Short Circuit Current		I_os	5	mA

NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot
    to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during
   transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional
    operation should be restricted to the conditions as detailed in the operational sections of this data
    sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

K9LAG08U0M Features

• Voltage Supply : 2.7 V ~ 3.6 V
• Organization
   - Memory Cell Array : (2G + 64M)bit x 8bit
   - Data Register : (2K + 64)bit x8bit
• Automatic Program and Erase
   - Page Program : (2K + 64)Byte
   - Block Erase : (256K + 8K)Byte
• Page Read Operation
   - Page Size : (2K + 64)Byte
   - Random Read : 60µs(Max.)
   - Serial Access : 30ns(Min.)
*K9MCG08U5M : 50ns(Min.)
• Memory Cell : 2bit / Memory Cell
• Fast Write Cycle Time
   - Program time : 800µs(Typ.)
   - Block Erase Time : 1.5ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
   - Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
   - Endurance : 5K Program/Erase Cycles(with 4bit/512byte ECC)
   - Data Retention : 10 Years
• Command Register Operation
• Unique ID for Copyright Protection
• Package :
   - K9LAG08U0M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
   - K9HBG08U1M-PCB0/PIB0 : Pb-FREE PACKAGE48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
   - K9HBG08U1M-ICB0/IIB0 52 - Pin TLGA (12 x 17 / 1.0 mm pitch)
   - K9MCG08U5M-PCB0/PIB0 : Two K9HBG08U0M package stacked 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) :
     Pb-FREE PACKAGE

K9LAG08U0M Connection Diagram

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