Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
The K7P403622B and K7P401822B are 4,718,592 bit Synchronous Pipeline Mode SRAM devices. They are organized as 131,072 words by 36 bits for K7P403622B and 262,144 words by 18 bits for K7P401822B, fabricated using Samsung's advanced CMOS technology.
Single differential PECL level K clocks or Single ended or differential LVTTL clocks are used to initiate read/write operation and all internal operations are self-timed. At the rising edge of K clock, Addresses, Write Enables,Synchronous Select and Data Ins are registered internally. Data outs are updated from output registers at the next rising edge of K clock. An internal write data buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
K7P403622B Maximum Ratings
Parameter
Symbol
Value
Unit
Core Supply Voltage Relative to VSS
VDD
-0.3 to 4.6
V
Output Supply Voltage Relative to VSS
VDDQ
VDD
V
Voltage on any I/O pin Relative to VSS
VTERM
-0.3 to VDD+0.3
V
Output Short-Circuit Current(per I/O)
IOUT
25
mA
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature
TSTR
-65 to 150
°C
NOTE : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
K7P403622B Features
• 128Kx36 or 256Kx18 Organizations. • 3.3V VDD, 2.5/3.3V VDDQ. • LVTTL Input and Output Levels. • Differential, PECL clock / Single ended or differential LVTTL clock Inputs • Synchronous Read and Write Operation. • Registered Input and Registered Output. • Internal Pipeline Latches to Support Late Write. • Byte Write Capability(four byte write selects, one for each 9bits) • Synchronous or Asynchronous Output Enable. • Power Down Mode via ZZ Signal. • JTAG Boundary Scan (subset of IEEE std. 1149.1). • 119(7x17)Pin Ball Grid Array Package(14mmx22mm).