K7D803671B, K7D803671B-H, K7D803671B-H25 Selling Leads, Datasheet
MFG:SIEMENS Package Cooled:BGA D/C:07+
K7D803671B, K7D803671B-H, K7D803671B-H25 Datasheet download
Part Number: K7D803671B
MFG: SIEMENS
Package Cooled: BGA
D/C: 07+
K7D803671B, K7D803671B-H, K7D803671B-H25
- Table of contents:
Info of K7D803671B
Info of K7D803671B-H
Info of K7D803671B-H25
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About K7D803671B
PDF/DataSheet Download
Datasheet: K7D803671B
File Size: 276613 KB
Manufacturer: SAMSUNG [Samsung semiconductor]
Download : Click here to Download
About K7D803671B-HC30
PDF/DataSheet Download
Datasheet: K7D803671B-HC30
File Size: 276613 KB
Manufacturer: SAMSUNG [Samsung semiconductor]
Download : Click here to Download
About K7D801871B-HC25
PDF/DataSheet Download
Datasheet: K7D801871B-HC25
File Size: 276613 KB
Manufacturer: SAMSUNG [Samsung semiconductor]
Download : Click here to Download
K7D803671B General Description
The K7D803671B and K7D801871B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 262,144 words by 36 bits for K7D803671B and 524,288 words by 18 bits for K7D801871B, fabricated using Samsung's advanced CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations, and off the rising and falling edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access time for all SDR and DDR operations.
The chip is operated with a single +2.5V power supply and is compatible with Extended HSTL input and output. The package is 9x17(153) Ball Grid Array balls on a 1.27mm pitch.
K7D803671B Maximum Ratings
| Parameter | Symbol | Value | Unit |
| Core Supply Voltage Relative to VSS | VDD | -0.5 to 3.13 | V |
| Output Supply Voltage Relative to VSS | VDDQ | -0.5 to 2.4 | V |
| Voltage on any pin Relative to VSS | VIN | -0.5 to VDDQ+0.5 (2.4V MAX) | V |
| Output Short-Circuit Current(per I/O) | IOUT | 25 | mA |
| Storage Temperature | TSTR | -55 to 125 | °C |
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
K7D803671B Features
• 256Kx36 or 512Kx18 Organizations.
• Maximum Frequency : 370MHz (Data Rate : 740Mbps)
• 2.5V VDD/1.5V VDDQ (2.0V max VDDQ).
• HSTL Input and Outputs.
• Single Differential HSTL Clock.
• Synchronous Pipeline Mode of Operation with Self-Timed Late Write.
• Free Running Active High and Active Low Echo Clock Output Pin.
• Asynchronous Output Enable.
• Registered Addresses, Burst Control and Data Inputs.
• Registered Outputs.
• Single and Double Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleved and Linear Burst mode support
• Bypass Operation Support
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).
• Maximum Frequency : 370MHz (Data Rate : 740Mbps)
• 2.5V VDD/1.5V VDDQ (2.0V max VDDQ).
• HSTL Input and Outputs.
• Single Differential HSTL Clock.
• Synchronous Pipeline Mode of Operation with Self-Timed Late Write.
• Free Running Active High and Active Low Echo Clock Output Pin.
• Asynchronous Output Enable.
• Registered Addresses, Burst Control and Data Inputs.
• Registered Outputs.
• Single and Double Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleved and Linear Burst mode support
• Bypass Operation Support
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).
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