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IS42S16320B-7TLI, IS42S16400, IS42S16400-10T

Table of contents:
Info of IS42S16320B-7TLI
Info of IS42S16400
Info of IS42S16400-10T

IS42S16320B-7TLI, IS42S16400, IS42S16400-10T Selling Leads, Datasheet

MFG:ISSI, Integrated Silicon Solution Inc Category:Integrated Circuits (ICs) Package Cooled:TSSOP D/C:1005

IS42S16320B-7TLI, IS42S16400, IS42S16400-10T Picture

IS42S16320B-7TLI, IS42S16400, IS42S16400-10T Datasheet download

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Part Number: IS42S16320B-7TLI

Category: Integrated Circuits (ICs)

MFG: ISSI, Integrated Silicon Solution Inc

Package Cooled: TSSOP

D/C: 1005

Description: IC SDRAM 512MB 143MHZ 54-TSOPII

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IS42S16320B-7TLI Parameters

Technical/Catalog Information	IS42S16320B-7TLI
Vendor	ISSI, Integrated Silicon Solution Inc
Category	Integrated Circuits (ICs)
Memory Type	SDRAM
Memory Size	512M (32Mx16)
Speed	143MHz
Interface	Parallel
Package / Case	54-TSOP II
Packaging	Tray
Voltage - Supply	3 V ~ 3.6 V
Operating Temperature	-40°C ~ 85°C
Format - Memory	RAM
Drawing Number	*
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	IS42S16320B 7TLI IS42S16320B7TLI

IS42S16400 General Description

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.

The 64Mb SDRAM includes an AUTO REFRESH MODE,and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.

The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.

A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and rovide seamless, high-speed, random-access operation. DRAM read and write accesses are burst oriented starting t a selected location and continuing for a programmed umber of locations in a programmed sequence. The egistration of an ACTIVE command begins accesses, ollowed by a READ or WRITE command. The ACTIVE ommand in conjunction with address bits registered are sed to select the bank and row to be accessed (BA0, BA1 elect the bank; A0-A11 select the row). The READ or RITE commands in conjunction with address bits registered re used to select the starting column location for he burst access.

Programmable READ or WRITE burst lengths consist of , 2, 4 and 8 locations or full page, with a burst terminate option.

IS42S16400 Maximum Ratings

Symbol	Parameters	Rating	Unit
V_{CC MAX}	Maximum Supply Voltage	1.0 to +4.6	V
V_{CCQ MAX}	Maximum Supply Voltage for Output Buffer	1.0 to +4.6	V
V_IN	Input Voltage	1.0 to +4.6	V
V_OUT	Output Voltage	1.0 to +4.6	V
P_{D MAX}	Allowable Power Dissipation	1	W
I_CS	Output Shorted Current	50	mA
T_OPR	Operating Temperature Com. Ind.	0 to +70 40 to +85
T_STG	Storage Temperature	55 to +150

IS42S16400 Features

• Clock frequency: 166, 133, 100 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
(1, 2, 4, 8, full page)
• Programmable burst sequence:Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Byte controlled by LDQM and UDQM
• Industrial temperature availability
• Package: 400-mil 54-pin TSOP II

IS42S16400 Connection Diagram

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