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ICS93V855AGLF, ICS93V857, ICS93V8571BG-130

Table of contents:
Info of ICS93V855AGLF
Info of ICS93V857
Info of ICS93V8571BG-130

ICS93V855AGLF, ICS93V857, ICS93V8571BG-130 Selling Leads, Datasheet

MFG:IDT, Integrated Device Technology Inc Category:Undefined Category Package Cooled:TSSOP-28 D/C:64

ICS93V855AGLF, ICS93V857, ICS93V8571BG-130 Picture

ICS93V855AGLF, ICS93V857, ICS93V8571BG-130 Datasheet download

Five Points

Part Number: ICS93V855AGLF

Category: Undefined Category

MFG: IDT, Integrated Device Technology Inc

Package Cooled: TSSOP-28

D/C: 64

Description: IC DDR PLL CLOCK DRIVER 28-TSSOP

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ICS93V855AGLF Parameters

Technical/Catalog Information	ICS93V855AGLF
Vendor	IDT, Integrated Device Technology Inc
Category	Undefined Category
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	ICS93V855AGLF ICS93V855AGLF

ICS93V857 Maximum Ratings

Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . .GND - 0.5V to VDD + 0.5V
Ambient Operating Temperature . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . .. -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

ICS93V857 Features

• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum tolerant inputs
• Auto PD when input signal removed
• Choice of static phase offset available, for easy board tuning;
   -XXX = device pattern number for options listed below.
   - ICS93V857-025 ...... 0ps
   - ICS93V857-125 +125ps
   - ICS93V857-130 .. +40ps

ICS93V857 Connection Diagram

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