Features: • 15 single ended LVCMOS outputs, 7 typical output impedance
• Selectable LVCMOS or LVPECL clock inputs
• CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
• PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Functionally compatible to the MPC949 in a smaller footprint requiring less board spacePinout
SpecificationsSupply Voltage, VDDx ....................4.6V
Inputs, VI...................... -0.5V to VDD + 0.5V
Outputs, VO .................-0.5V to VDD + 0.5V
Package Thermal Impedance, JA ......47.9°C/W (0 lfpm)
Storage Temperature, TSTG.......... -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DescriptionThe ICS01 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87949-01 has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs of the ICS01 are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines.
The divide select inputs of the ICS01, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/ nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.
The ICS01 is characterized at 3.3V core/3.3V output and 3.3V core/ 2.5V output. Guaranteed bank, output and part-topart skew characteristics make the ICS87949-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS01 Data Sheet
