HY500573222AFM-33, HY50U283222A, HY510N Selling Leads, Datasheet
MFG:30 Package Cooled:BGA D/C:08+/09+
HY500573222AFM-33, HY50U283222A, HY510N Datasheet download
Part Number: HY500573222AFM-33
MFG: 30
Package Cooled: BGA
D/C: 08+/09+
HY500573222AFM-33, HY50U283222A, HY510N
- Table of contents:
Info of HY500573222AFM-33
Info of HY50U283222A
Info of HY510N
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About HY50P
PDF/DataSheet Download
Datasheet: HY50P
File Size: 121146 KB
Manufacturer: LEM [LEM]
Download : Click here to Download
About HY50P
PDF/DataSheet Download
Datasheet: HY50P
File Size: 121146 KB
Manufacturer: LEM [LEM]
Download : Click here to Download
About HY50P
PDF/DataSheet Download
Datasheet: HY50P
File Size: 121146 KB
Manufacturer: LEM [LEM]
Download : Click here to Download
HY510N General Description
The HY510N provides protection circuits, power good output (PGO), fault protection latch (FPL_N),and a protection detector function (PDON_N) control. It can minimize external components of switching power supply systems in personal computer.
The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level. The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level. When OVD or UVD detect the fault voltage level,the FPL_N is latched HIGH and PGO go low. The latch can be reset by PDON_N goo HIGH. There is 2.4 ms delay time for PDON_N turn off FPL_N.
When OVD and UVD detect the right voltage level, the power good output (PGO) will be issue.
HY510N Features
` The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level.
` The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level.
` Both of the power good output (PGO) and fault protection latch (FPL_N) are Open Drain Output.
` 75 ms time delay for UVD.
` 300 ms time delay for PGO.
` 38 ms for PDON_N input signal Debounce.
` 73 us for internal signal Deglitches.
` 2.4 ms time delay for PDON_N turn-off FPL_N.
` ESD voltage up to 4000V as tested under MILSTD883D, Method 3015.7.
` The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level.
` Both of the power good output (PGO) and fault protection latch (FPL_N) are Open Drain Output.
` 75 ms time delay for UVD.
` 300 ms time delay for PGO.
` 38 ms for PDON_N input signal Debounce.
` 73 us for internal signal Deglitches.
` 2.4 ms time delay for PDON_N turn-off FPL_N.
` ESD voltage up to 4000V as tested under MILSTD883D, Method 3015.7.
HY510N Connection Diagram
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