H8SX/1651, H8X67-06, H900240ST Selling Leads, Datasheet
MFG:RENESAS Package Cooled:QFP D/C:09+
H8SX/1651, H8X67-06, H900240ST Datasheet download
Part Number: H8SX/1651
MFG: RENESAS
Package Cooled: QFP
D/C: 09+
H8SX/1651, H8X67-06, H900240ST
- Table of contents:
Info of H8SX/1651
Info of H8X67-06
Info of H900240ST
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About H8S/2140BF-ZTAT
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Datasheet: H8S/2140BF-ZTAT
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Manufacturer: RENESAS [Renesas Technology Corp]
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About H9018
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Datasheet: H9018
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Manufacturer: Shantou Huashan
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H8SX/1651 General Description
The H8SX CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16- bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system.
H8SX/1651 Maximum Ratings
| Item | Symbol | Value | Unit |
| Power supply voltage | VCC | 0.3 to +4.6 | V |
| Input voltage (except port 5) | Vin | 0.3 to VCC + 0.3 | V |
| Input voltage (port 5) | Vin | 0.3 to AVCC + 0.3 | V |
| Reference voltage | Vref | 0.3 to AVCC + 0.3 | V |
| Analog power supply voltage | AVCC | 0.3 to +4.6 | V |
| Analog input voltage | VAN | 0.3 to AVCC + 0.3 | V |
| Operating temperature | Topr | Regular specifications: 20 to +75 |
|
| Wide-range specifications: 40 to +85 |
|||
| Storage temperature | Tstg | 55 to +125 |
H8SX/1651 Features
• Upward-compatible with H8/300, H8/300H, and H8S CPUs
Can execute these CPU's object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• 87 basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Bit field transfer instructions
Powerful bit-manipulation instructions
Bit condition branch instructions
Multiply-and-accumulate instruction
• Eleven addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)]
Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W),
@(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)]
Register indirect with post-/pre-increment or post-/pre-decrement
[@+ERn/@−ERn/@ERn+/@ERn−]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or @(ERn.L,PC)]
Memory indirect [@@aa:8]
Extended memory indirect [@@vec:7]
• Two base registers
Vector base register
Short address base register
• 4-Gbyte address space
Program: 4 Gbytes
Data: 4 Gbytes
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 1 state
16 ÷ 8-bit register-register divide: 10 states
16 × 16-bit register-register multiply: 1 state
32 ÷ 16-bit register-register divide: 18 states
32 × 32-bit register-register multiply: 5 states
32 ÷ 32-bit register-register divide: 18 states
• Four CPU operating modes
Normal mode
Middle mode
Advanced mode
Maximum mode
• Power-down modes
Transition is made by execution of SLEEP instruction
Choice of CPU operating clocks
Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1651 Group. Normal, middle, and maximum modes are not supported.
2. The multiplier and divider are supported by the H8SX/1651 Group.
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