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The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V.
GTLP18T612 Maximum Ratings
Product
Product status
Eco Status
Pricing*
Package type
Leads
Packing method
Package Drawing
Package Marking Convention**
GTLP18T612MEA
Full Production
Green
$8.31
SSOP
56
RAIL
Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP18T612
GTLP18T612MEAX
Full Production
Green
$8.31
SSOP
56
TAPE REEL
Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP18T612
GTLP18T612MTD
Full Production
RoHS Compliant
$8.31
TSSOP
56
RAIL
Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP18T612
GTLP18T612MTDX
Full Production
RoHS Compliant
$8.31
TSSOP
56
TAPE REEL
Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP18T612
* Fairchild 1,000 piece Budgetary Pricing
** A sample button will appear if the part is available through Fairchild's on-line samples program. If there is no sample button, please contact a Fairchild distributor to obtain samples
Package marking information for product GTLP18T612 is available. Click here for more information .
GTLP18T612 Features
Bidirectional interface between GTLP and LVTTL logiclevels Edge Rate Control to minimize noise on the GTLP port Power up/down high impedance for live insertion External VREF pin for receiver threshold BiCMOS technology for low power dissipation Bushold data inputs on A Port eliminates the need for external pull-up resistors for unused inputs LVTTL compatible Driver and Control inputs Flow-through architecture optimizes PCB layout Open drain on GTLP to support wired-or connection A-Port source/sink −24 mA/+24 mA B-Port sink capability +50 mA D-type flip-flop, latch and transparent data paths