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The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control which minimizes signal settling times. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V and the receiver threshold is 1.0V.
GTLP16612 Maximum Ratings
Product
Product status
Eco Status
Pricing*
Package type
Leads
Packing method
Package Drawing
Package Marking Convention**
GTLP16612MEA
Full Production
Green
$5.71
SSOP
56
RAIL
Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP16612
GTLP16612MEAX
Full Production
Green
$5.71
SSOP
56
TAPE REEL
Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP16612
GTLP16612MTD
Full Production
RoHS Compliant
$5.71
TSSOP
56
RAIL
Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP16612
GTLP16612MTDX
Full Production
RoHS Compliant
$5.71
TSSOP
56
TAPE REEL
Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP16612
* Fairchild 1,000 piece Budgetary Pricing
** A sample button will appear if the part is available through Fairchild's on-line samples program. If there is no sample button, please contact a Fairchild distributor to obtain samples
Package marking information for product GTLP16612 is available. Click here for more information .
GTLP16612 Features
Bidirectional interface between GTLP and TTL logiclevels Designed with Edge Rate Control Circuit to reduceoutput noise VREF pin provides external supply reference voltage forreceiver threshold Submicron Core CMOS technology for low powerdissipation Special PVT Compensation circuitry to provide consis- tent performance over variations of process, supplyvoltage and temperature 5V tolerant inputs and outputs on A-Port Bus-Hold data inputs on A-Port to eliminate the need for external pull-up resistors for unused inputs Power up/down high impedance TTL compatible Driver and Control inputs A-Port outputs source/sink −32 mA/+32 mA Flow-through architecture optimizes PCB layout Open drain on GTLP to support wired-or connection