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The GTLP10B320 is a 10-bit Universal bus driver andreceiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL t GTLP signal level translation. High speed backplane oper ation is a direct result of GTLP!s reduced output swi (<1V), reduced input threshold levels and output edge rat control. The edge rate control minimizes bus settling time GTLP is a Fairchild Semiconductor derivative of th Gunning Transistor logic (GTL) JEDEC standard JESD8-3 Fairchild!s GTLP has internal edge-rate control and is pr cess, voltage and temperature (PVT) compensated. It function is similar to BTL and GTL but with different outpu levels and receiver threshold. GTLP output low level is typ ically less than 0.5V, the output level high is 1.5V and th receiver threshold is 1.0V.
GTLP10B320 Maximum Ratings
Supply Voltage (VCC ) ......-0.5V to +4.6V DC Input Voltage (VI) ......-0.5V to +4.6V DC Output Voltage (VO)... ..-0.5V to +4.6V Outputs 3-STATE Outputs Active (Note 6) ..... 0.5V to +4.6V DC Output Sink Current into C Port IOL ..................48 mA
DC Output Source Current from C Port IOH................48 mA
DC Output Sink Current into
B Port in the LOW State, IOL......100 mA
DC Input Diode Current (IIK) < 0V ... 50 mA DC Output Diode Current (IOK ). < 0V -50 mA VO < 0V ................. 50 mA ESD Rating...............>2000V
Storage Temperature (TSTG) .-65 to +150
GTLP10B320 Features
·Bidirectional interface between GTLP and LVTTL logiclevels ·Variable edge rate control pin to select desired edge rateon GTLP port (V)ERC ·VREFpin provides external supplreceiver threshold adjustibility ·Split LVTTL inputs and outputs ·Special PVT compensation circuitry to provide consis-tent performance over variations of process, supply volt-age and temperature ·A feedback path for control and diagnostics monitoring ·TTL compatible driver and control inputs ·Designed using Fairchild advanced BiCMOS technology ·Bushold data inputs on A port to eliminate the need forexternal pull-up resistors for unused inputs ·Power up/down and power off high impedance for liveinsertion ·Open drain on GTLP to support wired-or connection ·Flow through pinout optimizes PCB layout ·A Port source/sink -24mA/+24mA ·B Port sink +50mA