GDBJ001, GDC21D301A, GDC21D401B Selling Leads, Datasheet
MFG:ST Package Cooled:SOP-20L D/C:06+
GDBJ001, GDC21D301A, GDC21D401B Datasheet download
Part Number: GDBJ001
MFG: ST
Package Cooled: SOP-20L
D/C: 06+
GDBJ001, GDC21D301A, GDC21D401B
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Info of GDBJ001
Info of GDC21D301A
Info of GDC21D401B
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About GDC21D301A
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Datasheet: GDC21D301A
File Size: 882652 KB
Manufacturer: HYNIX [Hynix Semiconductor]
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About GDC21D401B
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Datasheet: GDC21D401B
File Size: 710801 KB
Manufacturer: HYNIX [Hynix Semiconductor]
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GDC21D301A General Description
The GDC21D301A Transport Decoder resides in the center of an MPEG-2 decoding system. It accepts MPEG-2 transport streams, parses the transport and packetized elementary stream (PES) layers into the separate data streams, and provides rate buffering for the parsed data streams. Then it passes those data streams to video and audio decoders. The GDC21D301A also extracts Program Clock Reference (PCR) in the data stream and provides the Pulse Width
Modulation (PWM) signals in order to recover the clock and to synchronize the playback of video and audio. The GDC21D301A manages an external DRAM that is used for data storage and buffering the various parsed data streams. This DRAM is shared with the host processor so that the system's memory requirements can be consolidated into a single, low-cost DRAM. The GDC21D301A stores data packets destined for the host directly in shared DRAM for easy access by the host.
GDC21D301A Maximum Ratings
|
SYMBOL |
PARAMETERS |
VALUES |
UNIT |
|
VDD |
Power Supply Voltage |
-0.33 to 5.5 |
V |
|
VI |
Digital Input Voltage |
-0.33 to VDD + 0.5 |
V |
|
Vo |
Digital Output Voltage |
-0.33 to VDD + 0.5 |
V |
|
Tstg |
Storage Temperature |
-55 to 125 |
`` |
|
Pd |
Power Dissipation |
1.0 |
W |
Note : Absolute Maximum Ratings means that the safety of the device cannot be guaranteed beyond these values and it doesn't imply that the device
should be operated within these limits.
GDC21D301A Features
The GDC21D301A is fully compliant with MPEG- 2 ISO/IEC 13818-1 specification.
Decoding Features
· Performs MPEG-2 transportation and PES layer handling
· Supports maximum 80 Mbps transport streams
· Provides a high-speed data output port
· Identifies and extracts up to 32 transport stream (TS) packet PIDs
PCR & Time Stamp Control Features
· Provides two PWM signals to recover the system clock
· Provides the instant value of internal STC counter when a frame begins
· Extracts PTS and DTS of video and audio for Lip-synchronization Interface
· Supports byte-parallel/bit-serial TS input
· Supports video/audio PES layer or elementary stream layer output
· Provides error code insertion capability in video elementary stream
· Supports an external error input signal for declaring an erroneous packet
· Supports 8/16-bit host bus interface
Decoding Features
· Performs MPEG-2 transportation and PES layer handling
· Supports maximum 80 Mbps transport streams
· Provides a high-speed data output port
· Identifies and extracts up to 32 transport stream (TS) packet PIDs
PCR & Time Stamp Control Features
· Provides two PWM signals to recover the system clock
· Provides the instant value of internal STC counter when a frame begins
· Extracts PTS and DTS of video and audio for Lip-synchronization Interface
· Supports byte-parallel/bit-serial TS input
· Supports video/audio PES layer or elementary stream layer output
· Provides error code insertion capability in video elementary stream
· Supports an external error input signal for declaring an erroneous packet
· Supports 8/16-bit host bus interface
GDC21D301A Connection Diagram
GDC21D401B General Description
The Video Decoder(VD) decodes video elementary stream of MPEG-2(ISO/ICE 13818-2)MP@HL. It supports the ATSC digital TV video standard, and can be used for the video part of the ATSC digital TV with the Transport Decoder and the VDP(Video Display Processor). Picture decoding timing can be controlled internally for A/V lip synchronization, and externally for Video Trick Mode by host microprocessor via I2C bus. The Video Decoder can extract video user data including caption from video elementary stream, and host microprocessor can read the video user data from the Video Decoder(VD) via I2C. It uses four 16x1M SDRAMs and can support up to 81 MHz memory clock speed.
GDC21D401B Maximum Ratings
|
SYMBOL |
PARAMETERS |
VALUES |
UNIT |
|
VDD |
Power Supply Voltage |
-0.33 to 5.5 |
V |
|
VI |
Digital Input Voltage |
-0.33 to VDD + 0.5 |
V |
|
Vo |
Digital Output Voltage |
-0.33 to VDD + 0.5 |
V |
|
Tstg |
Storage Temperature |
-55 to 125 |
|
|
Pd |
Power Dissipation |
4.6 |
W |
*Note :Absolute Maximum Ratings mean that the safety of the device cannot be guaranteed beyond these values, and this doesn't imply that the device should be operated within these limits.
GDC21D401B Features
· Supports MPEG-2 (ISO/ICE 13818-2) MP@HL
· Supports all video input formats of ATSC digital TV standard
· Supports picture decoding capability up to 1920x1088 30 Frame/Sec
· Supports all kinds of motion compensation methods of MPEG-2
· Supports MPEG-2 error code, syntax error
detection, and slice-based error concealment
· Supports DTS synchronization
· Supports VBV delay mode and low delay mode decoding
· Supports film mode decoding (3:2 Pull down)
· Supports high level commands for trick mode
· Supports 8(w)x64(d) internal user data FIFO
· Outputs: macroblock format
4-pel parallel output
54 MHz synchronous I/F
Data window (pdwin, sclk, and mbclk)
Picture information (Picture structure, Field
parity, and DCT type)
· External memory for VBV buffer , DTS
FIFO and 2-frame memory:
64-bit Data Bus
81 MHz Synchronous Interface
64-Mbyte
Four 16x1M SDRAMs
· Host processor interface: I2C bus interface
Two interrupt signals
Supports 23 programmable internal
registers
· Supports all video input formats of ATSC digital TV standard
· Supports picture decoding capability up to 1920x1088 30 Frame/Sec
· Supports all kinds of motion compensation methods of MPEG-2
· Supports MPEG-2 error code, syntax error
detection, and slice-based error concealment
· Supports DTS synchronization
· Supports VBV delay mode and low delay mode decoding
· Supports film mode decoding (3:2 Pull down)
· Supports high level commands for trick mode
· Supports 8(w)x64(d) internal user data FIFO
· Outputs: macroblock format
4-pel parallel output
54 MHz synchronous I/F
Data window (pdwin, sclk, and mbclk)
Picture information (Picture structure, Field
parity, and DCT type)
· External memory for VBV buffer , DTS
FIFO and 2-frame memory:
64-bit Data Bus
81 MHz Synchronous Interface
64-Mbyte
Four 16x1M SDRAMs
· Host processor interface: I2C bus interface
Two interrupt signals
Supports 23 programmable internal
registers
GDC21D401B Connection Diagram
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