DS3890N, DS3892N, DS3893A Selling Leads, Datasheet
MFG:NS Package Cooled:NS D/C:98+
DS3890N, DS3892N, DS3893A Datasheet download
Part Number: DS3890N
MFG: NS
Package Cooled: NS
D/C: 98+
MFG:NS Package Cooled:NS D/C:98+
DS3890N, DS3892N, DS3893A Datasheet download
MFG: NS
Package Cooled: NS
D/C: 98+
Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
TOP
PDF/DataSheet Download
Datasheet: DS3890N
File Size: 186350 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: DS3892N
File Size: 186350 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: DS3893A
File Size: 632946 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
The TURBOTRANSCEIVER is designed for use in very highspeed bus systems. The bus terminal characteristics of theTURBOTRANSCEIVER are referred to as "BackplaneTransceiver Logic" (BTL). BTL is a new logic signaling stan-dard that has been developed to enhance the performanceof backplane buses. BTL compatible transceivers featurelow output capacitance drivers to minimize bus loading, a 1Vnominal signal swing for reduced power consumption andreceivers with precision thresholds for maximum noise im-munity. This new standard eliminates the settling time de-lays, that severely limit the TTL bus performance, to providesignificantly higher bus transfer rates.
The TURBOTRANSCEIVER is compatible with the require-ments of the proposed IEEE 896 Futurebus draft standard. Itis similar to the DS3896/97 BTL TRAPEZOIDAL™ Trans-ceivers but the trapezoidal feature has been removed toimprove the propagation delay. A stripline backplane is there-fore required to reduce the crosstalk induced by the fasterrise and fall times. This device can drive a 10Ω load with atypical propagation delay of 3.5 ns for the driver and 5 ns forthe receiver.
When multiple devices are used to drive a parallel bus, thedriver enables can be tied together and used as a commoncontrol line to get on and off the bus. The driver enable delayis designed to be the same as the driver propagation delay inorder to provide maximum speed in this configuration. Thelow input current on the enable pin eases the drive requiredfor the common control line.
The bus driver is an open collector NPN with a Schottkydiode in series to isolate the transistor output capacitancefrom the bus when the driver is in the inactive state. Theactive output low voltage is typically 1V. The bus is intendedto be operated with termination resistors (selected to matchthe bus impedance) to 2.1V at both ends. Each of theresistors can be as low as 20Ω.