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DS33X162, DS33Z11, DS33Z44

Table of contents:
Info of DS33X162
Info of DS33Z11
Info of DS33Z44

DS33X162, DS33Z11, DS33Z44 Selling Leads, Datasheet

MFG:DALLAS Package Cooled:BGA D/C:N/A

DS33X162, DS33Z11, DS33Z44 Datasheet download

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Part Number: DS33X162

MFG: DALLAS

Package Cooled: BGA

D/C: N/A

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DS33Z11 General Description

The DS33Z11 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86 (LAPS) mapper, SDRAM interface, control ports, and bit error-rate tester (BERT). The packet interface consists of an Ethernet interface using several physical-layer protocols. The Ethernet interface can be configured for 10 Mbps or 100 Mbps service. The DS33Z11 encapsulates Ethernet traffic with HDLC or X.86 (LAPS) to be transmitted over the WAN interface. The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the Ethernet port. The WAN physical interface supports a serial data stream up to 52 Mbps. The WAN interface can be seamlessly connected to the Dallas Semiconductor/Maxim T1/E1/J1 framers, line interface units (LIUs), and single-chip transceivers (SCTs). The WAN interface can also be seamlessly connected to the Dallas Semiconductor/Maxim T3/E3/STS-1 framers, LIUs, and SCTs to provide T3, E3, and STS1 connectivity. Refer to Application Note 3411: DS33Z11óEthernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete LAN to WAN solution.

The DS33Z11 is controlled through an 8-bit microcontroller port. A serial EEPROM (SPI) interface and hardware mode are also included for applications without a host processor. The DS33Z11 has a 100MHz SDRAM controller and interfaces to a 32-bit wide 128 Mbit SDRAM. The SDRAM is used to buffer the data from the Ethernet and WAN ports for transport. The external SDRAM can accommodate up to 8192 frames with a maximum frame size of 2016 bytes.

Operation without an external host simplifies and reduces the cost of typical applications such as connectivity to T1/T3 and E1/E3 front ends. The DS33Z11 operates with a 1.8V core supply and 3.3V I/O supply.

DS33Z11 Maximum Ratings

Voltage Range on Any Lead with Respect to VSS (except V_DD).............................0.5V to +5.5V
Supply Voltage Range (VDD3.3) with Respect to V_SS............................................0.3V to +3.6V
Supply Voltage Range (VDD1.8) with Respect to V_SS............................................0.3V to +2.0V
Ambient Operating Temperature Range.................................................................40 to +85
Junction Operating Temperature Range............................................................. ..40to +125
Storage Temperature Range................................................................................55 to +125
Soldering Temperature....................................................See IPC/JEDEC J-STD-020 Specification

DS33Z11 Features

10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
52Mbps Synchronous TDM Serial Port with Independent Transmit and Receive Timing
HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill
Committed Information Rate Controller Provides Fractional Allocations in 512kbps Increments
Programmable BERT for Serial (TDM) Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
SPI Interface and Hardware Mode for Operation Without a Host Processor
Also Available in a 100-Ball, 10mm CSBGAóthe Hardware/SPI Mode-Only DS33ZH11
1.8V Operation with 3.3V Tolerant I/O
IEEE 1149.1 JTAG Support

DS33Z11 Typical Application

The DS33Z11 is designed for use in the following applications:
·Transparent LAN Service
·LAN Extension
·Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4

Refer also to Application Note 3411: DS33Z11óEthernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete LAN to WAN design.

DS33Z44 General Description

The DS33Z44 extends four 10/100 Ethernet LAN segments by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over four PDH/TDM data streams. The serial links support bidirectional synchronous interconnect up to 52Mbps over xDSL, T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or SONET/SDH Tributary.

The device performs store-and-forward of packets with full wire-speed transport capability. The built-in Committed Information Rate (CIR) controllers provide fractional bandwidth allocation up to the line rate in increments of 512kbps. The DS33Z44 can operate with an inexpensive external processor, EEPROM or in a stand-alone hardware mode.

DS33Z44 Maximum Ratings

Voltage Range on Any Lead with Respect to VSS (except V_DD)........-0.5V to +5.5V
Supply Voltage Range (V_DD3.3) with Respect to V_{SS........................}-0.3V to +3.6V
Supply Voltage Range (V_DD1.8) with Respect to V_{SS........................}-0.3V to +2.0V
Ambient Operating Temperature Range.........................................-40°C to +85°C
Junction Operating Temperature Range.......................................-40°C to +125°C
Storage Temperature...................................................................-55°C to +125°C
Soldering Temperature...............................See IPC/JEDEC J-STD-020 Specification

These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. Ambient Operating Temperature Range is assuming the device is mounted on a JEDEC-standard test board in a convection-cooled JEDEC test enclosure.

Note: The *typ* values listed below are not production tested.

DS33Z44 Features

· Four 10/100 IEEE 802.3 Ethernet MACs (MII and RMII) Half/Full Duplex with Automatic Flow Control
· Four 52Mbps Synchronous TDM Serial Ports with independent transmit and receive timing.
· HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill
· Committed Information Rate Controllers Provide Fractional Allocations in 512kbps Increments
· Programmable BERT for Serial (TDM) Interfaces
· External 16MB, 100MHz SDRAM Buffering
· Parallel Microprocessor Interface
· SPI Interface and Hardware Mode for Operation Without a Host Processor
· 1.8V Operation with 3.3V Tolerant I/O
· IEEE 1149.1 JTAG Support

DS33Z44 Typical Application

· Transparent LAN Service
· LAN Extension Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4

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