DP83255AVF258, DP83256, DP83257 Selling Leads, Datasheet
MFG:4800 Package Cooled:QFP-100 D/C:N/A
DP83255AVF258, DP83256, DP83257 Datasheet download
Part Number: DP83255AVF258
MFG: 4800
Package Cooled: QFP-100
D/C: N/A
DP83255AVF258, DP83256, DP83257
- Table of contents:
Info of DP83255AVF258
Info of DP83256
Info of DP83257
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About DP802518
PDF/DataSheet Download
Datasheet: DP802518
File Size: 167262 KB
Manufacturer: National Semiconductor
Download : Click here to Download
About DP83256
PDF/DataSheet Download
Datasheet: DP83256
File Size: 1019921 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
About DP83257VF
PDF/DataSheet Download
Datasheet: DP83257VF
File Size: 1019921 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
DP83256 General Description
The DP8325656-AP57 Enhanced Physical Layer Controller (PLAYER +device) implements one complete Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T95 standard
The PLAYER +device integrates state of the art digital clock recovery and improved clock generation functions to
enhance performance eliminate external components and remove critical layout requirements
FDDI Station Management (SMT) is aided by Link ErrorMonitoring support Noise Event Timer (TNE) support Optional Auto Scrubbing support an integrated configuration switch and built-in functionality designed to remove all stringent response time requirements such as PC React and CF React
The PLAYER +device integrates state of the art digital clock recovery and improved clock generation functions to
enhance performance eliminate external components and remove critical layout requirements
FDDI Station Management (SMT) is aided by Link ErrorMonitoring support Noise Event Timer (TNE) support Optional Auto Scrubbing support an integrated configuration switch and built-in functionality designed to remove all stringent response time requirements such as PC React and CF React
DP83256 Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
|
VCC |
SupplyVoltage |
|
-0.5 |
|
70 |
V |
|
DCIN |
InputVoltage |
|
-0.5 |
|
VCC +0.5 |
V |
|
DCOUT |
OutputVoltage |
|
-0.5 |
|
VCC+ 0.5 |
V |
|
|
VCCESDtootherVCC
MaximumVoltage
Differential |
|
|
|
0.3 |
V |
|
|
StorageTemperature |
|
-65 |
|
150 |
|
|
ECL |
SignalOutputCurrent |
|
|
|
-50 |
mA |
|
|
ESDProtection |
|
2000 |
|
|
V |
DP83256 Features
Single chip FDDI Physical Layer (PHY) solution
Integrated Digital Clock Recovery Module provides enhanced tracking and greater lock acquisition range
Integrated Clock Generation Module provides all necessary clock signals for an FDDI system from an external 125 MHz reference
Alternate PMD Interface (DP83256-AP57) supports UTP twisted pair FDDI PMDs with no external clock recovery or clock generation functions required
No External Filter Components
Connection Management (CMT) Support (LEM TNEPC React CF React Auto Scrubbing)
Full on-chip configuration switch
Low Power CMOS-BIPOLAR design using a single 5V supply
Full duplex operation with through parity
Separate management interface (Control Bus)
Selectable Parity on PHY-MAC Interface and Control Bus Interface
Two levels of on-chip loopback
4B/5B encoderdecoder
Framing logic
Elasticity Buffer Repeat Filter and Smoother
Line state detectorgenerator
Supports single attach stations dual attach stations
and concentrators with no external logic
DP83256 for SASDAS single path stations
DP83257 for SASDAS singledual path stations
DP83256-AP for SASDAS single path stations that require the alternate PMD interface
DP83256 Connection Diagram
DP83257 General Description
The DP8325656-AP57 Enhanced Physical Layer Controller (PLAYER +device) implements one complete Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T95 standard
The PLAYER +device integrates state of the art digital clock recovery and improved clock generation functions to
enhance performance eliminate external components and remove critical layout requirements
FDDI Station Management (SMT) is aided by Link ErrorMonitoring support Noise Event Timer (TNE) support Optional Auto Scrubbing support an integrated configuration switch and built-in functionality designed to remove all stringent response time requirements such as PC React and CF React
The PLAYER +device integrates state of the art digital clock recovery and improved clock generation functions to
enhance performance eliminate external components and remove critical layout requirements
FDDI Station Management (SMT) is aided by Link ErrorMonitoring support Noise Event Timer (TNE) support Optional Auto Scrubbing support an integrated configuration switch and built-in functionality designed to remove all stringent response time requirements such as PC React and CF React
DP83257 Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
|
VCC |
SupplyVoltage |
|
-0.5 |
|
70 |
V |
|
DCIN |
InputVoltage |
|
-0.5 |
|
VCC +0.5 |
V |
|
DCOUT |
OutputVoltage |
|
-0.5 |
|
VCC+ 0.5 |
V |
|
|
VCCESDtootherVCC
MaximumVoltage
Differential |
|
|
|
0.3 |
V |
|
|
StorageTemperature |
|
-65 |
|
150 |
|
|
ECL |
SignalOutputCurrent |
|
|
|
-50 |
mA |
|
|
ESDProtection |
|
2000 |
|
|
V |
DP83257 Features
Single chip FDDI Physical Layer (PHY) solution
Integrated Digital Clock Recovery Module provides enhanced tracking and greater lock acquisition range
Integrated Clock Generation Module provides all necessary clock signals for an FDDI system from an external 125 MHz reference
Alternate PMD Interface (DP83256-AP57) supports UTP twisted pair FDDI PMDs with no external clock recovery or clock generation functions required
No External Filter Components
Connection Management (CMT) Support (LEM TNEPC React CF React Auto Scrubbing)
Full on-chip configuration switch
Low Power CMOS-BIPOLAR design using a single 5V supply
Full duplex operation with through parity
Separate management interface (Control Bus)
Selectable Parity on PHY-MAC Interface and Control Bus Interface
Two levels of on-chip loopback
4B/5B encoderdecoder
Framing logic
Elasticity Buffer Repeat Filter and Smoother
Line state detectorgenerator
Supports single attach stations dual attach stations
and concentrators with no external logic
DP83256 for SASDAS single path stations
DP83257 for SASDAS singledual path stations
DP83256-AP for SASDAS single path stations that require the alternate PMD interface
DP83257 Connection Diagram
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