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CYNSE20512, CYNSE20512-2662FGC, CYNSE20512A-133FGC

Table of contents:
Info of CYNSE20512
Info of CYNSE20512-2662FGC
Info of CYNSE20512A-133FGC

CYNSE20512, CYNSE20512-2662FGC, CYNSE20512A-133FGC Selling Leads, Datasheet

MFG:CYPRESS Package Cooled:N/A D/C:09+

CYNSE20512, CYNSE20512-2662FGC, CYNSE20512A-133FGC Picture

CYNSE20512, CYNSE20512-2662FGC, CYNSE20512A-133FGC Datasheet download

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Part Number: CYNSE20512

MFG: CYPRESS

Package Cooled: N/A

D/C: 09+

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CYNSE20512 General Description

The high-speed Ayama 20000 family of NSEs can be deployed in a variety of networking and communications applications. The performance and features of this family make it attractive in applications such as enterprise LAN switches, routing equipment, and security applications. The Ayama 20000 family of high-speed search engines are capable of supporting network data rates in excess of 10 Gbps.

The Ayama 20000 network search engine (NSE) provides a seamless connection to commercial packet processors via the industry-standard Look Aside (LA-1) Interface. The Ayama 20000 consists of control logic, which processes the commands, and a full Ternary Content-Addressable Memory (TCAM) array, which stores the databases searched by the control logic. Figure 1 shows a block diagram of the Ayama 20000. The Ayama 20000 family includes densities of 18-Mbit (512k entries) and 9-Mbit (256k entries).

Using its two LA-1 ports, the Ayama 20000 NSE can interface with one or two packet processors. The processor issues commands and the Ayama 20000 returns the results of execution via this interface. One port may be connected to an ingress packet processor and the other to an egress packet processor. Both packet processors can perform searches on the same databases, eliminating the need for redundant memories or NSEs.

This family is designed to be scalable to support large databases. Through the FastLink Interface, the Ayama 20000 can access both the Ayama 10000 and the Sahasra 50000 NSEs.

CYNSE20512 Maximum Ratings

Storage Temperature, condition B ...............65°C to +150°C
Maximum Junction Temperature .......................125°C
Static Discharge Voltage
(Human Body Model,
JEDEC EIA./JESD22-A114B,
MIL-STD-883E-3015).............................>2000V
ESD CDM Model (EIA/JESD22-C101C)......................500V
Latch-up Current (EIA/JESD17).......................+ 300mA

CYNSE20512 Features

• Fast search rates
   - Up to 266 million searches per second (MSPS) in
   72/144-bit configuration using MultiSearch™
   - Up to 133 MSPS in 32/288-bit configuration
   - Up to 66.5 MSPS in 576-bit configuration
• High packet processor transfer efficiency on the LA-1 Interface
   - 32-bit searches
   - Searches that reuse previous search keys using Key Capture™
   - Interrupt-driven Result Available signal saves
   polling cycles for result retrieval
• Mini-Key™ feature reduces power consumption by
   enabling only relevant blocks during a search
• Associated Data Management enables efficient SRAM management
• Ability to search two tables in a single clock cycle using MultiSearch
• Learn command simplifies data plane updates
• Ease of table management
   - Soft Priority™, assignable per sub-block
   - Mini-Key assignable per block
   - Cynapse™ APIs facilitate table management
• Aging of up to 256k entries using AgeAssist™
   - Age up to four independent tables
   - Single or double-buffered tables
• Atomic Command enables uninterrupted execution for
   a sequence of commands
• Error Management
   - Parity per interface
   - Core parity for data and mask arrays
   - Maskable error interrupt signal to the packet processor
• Cascadable for storage expansion with external NSEs
   using FastLink Interface
   - Logically expandable to store up to 25 million entries
   - Supports Ayama™ 10000 and/or Sahasra™ 50000 NSEs
• NPF-compatible Look-Aside (LA-1) Interface
   - One or two LA-1 ports
   - Support for 128 contexts per LA-1 port
   - QDR-II up to 250 MHz, Burst-of-2 and Burst-of-4
   - Convenient "Clamshellable" pinout for ease of board design
• No Bus Latency™ (NoBL™) SRAM Interface
   - 1.5V HSTL or 1.8V/2.5V LVCMOS I/Os support up to 200 MHz
• FastLink Interface
   - 1.5V HSTL I/Os support up to 266 MHz
   - 1.8V/2.5V LVCMOS I/Os support up to 200 MHz
• Configurable internal NSE table sizes
   - 512k entries in 36-bit configuration
   - 256k entries in 72-bit configuration
   - 128k entries in 144-bit configuration
   - 64k entries in 288-bit configuration
   - 32k entries in 576-bit configuration
• IEEE 1149.1 JTAG test access port
• 1.2V Core supply
• 1152-ball 35mm x 35mm FBGA package

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