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CDC516DGGR, CDC528, CDC536

Table of contents:
Info of CDC516DGGR
Info of CDC528
Info of CDC536

CDC516DGGR, CDC528, CDC536 Selling Leads, Datasheet

MFG:Texas Instruments (VA) Category:Integrated Circuits (ICs) Package Cooled:TSSOP48 D/C:01+

CDC516DGGR, CDC528, CDC536 Datasheet download

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Part Number: CDC516DGGR

Category: Integrated Circuits (ICs)

MFG: Texas Instruments (VA)

Package Cooled: TSSOP48

D/C: 01+

Description: IC 3.3V PLL CLK DRVR 3ST 48TSSOP

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CDC516DGGR Parameters

Technical/Catalog Information	CDC516DGGR
Vendor	Texas Instruments (VA)
Category	Integrated Circuits (ICs)
Type	PLL Clock Driver
Voltage - Supply	3 V ~ 3.6 V
Number of Outputs	16
Input	LVTTL
Output	LVTTL
Frequency-Max	125MHz
Package / Case	48-TSSOP
Packaging	Cut Tape (CT)
Operating Temperature	0°C ~ 70°C
Drawing Number	296; 4040078; DGG; 48, 56, 64
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CDC516DGGR CDC516DGGR 296 6706 1 ND 29667061ND 296-6706-1

CDC516DGGR General Description

3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options

CDC516DGGR Features

Low-Output Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V V_CC
Distributes One Clock Input to Six Outputs
One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
No External RC Network Required
External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
Application for Synchronous DRAM, High-Speed Microprocessor
Negative-Edge-Triggered Clear for Half-Frequency Outputs
TTL-Compatible Inputs and Outputs
Outputs Drive 50- Parallel-Terminated Transmission Lines
State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
Distributed V_CC and Ground Pins Reduce Switching Noise
Packaged in Plastic 28-Pin Shrink Small Outline Package

CDC516DGGR Typical Application

CDC536 Datasheet

CDC536 Parameters

CDC536 Features

Low-Output Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V V_CC
Distributes One Clock Input to Six Outputs
One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
No External RC Network Required
External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
Application for Synchronous DRAM, High-Speed Microprocessor
Negative-Edge-Triggered Clear for Half-Frequency Outputs
TTL-Compatible Inputs and Outputs
Outputs Drive 50- Parallel-Terminated Transmission Lines
State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
Distributed V_CC and Ground Pins Reduce Switching Noise
Packaged in Plastic 28-Pin Shrink Small Outline Package

CDC536 General Description

3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options

CDC536 Features

Low-Output Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V V_CC
Distributes One Clock Input to Six Outputs
One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
No External RC Network Required
External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
Application for Synchronous DRAM, High-Speed Microprocessor
Negative-Edge-Triggered Clear for Half-Frequency Outputs
TTL-Compatible Inputs and Outputs
Outputs Drive 50- Parallel-Terminated Transmission Lines
State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
Distributed V_CC and Ground Pins Reduce Switching Noise
Packaged in Plastic 28-Pin Shrink Small Outline Package

CDC536 Typical Application

CDC536 Datasheet

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