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?ROHM's high reliability serial EEPROMs command a large market share and are available in a range of capacities, bus interfaces (Microwire, I2C, SPI), operating voltages (1.8V to 5.5V, 2.5V to 5.5V) and package types, making them ideal for battery powered devices. In addition, the entire series utilizes unique double cell construction, significantly improving reliability, and are both lead-free and RoHS-compliant.
BR24L04 Maximum Ratings
I/F
I2C BUS
Capacity (K)
4
Bit Format
512×8
Supply Voltage (V)
1.8 to 5.5
Current consumption
Operating(mA)
2
Standby(µA)
2
Max.Write Cycle Time (ms)
5
Operating Temperature Range (ºC)
-40 to +85
Number of Rewrite (Times)
106
Data Retention (Years)
40
BR24L04 Connection Diagram
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BR24L04FV-W General Description
The BR24L04-W series is 2-wire (I2 C BUS type) serial EEPROMs which are electrically programmable.
BR24L04FV-W Maximum Ratings
Parameter
Symbol
Limits
Unit
Supply voltage
VCC
-0.3 to +6.5
V
Power dissipation
Pd
800(DIP8) *1
mW
450(SOP8) *2
450(SOP-J8) *2
300(SSOP-B8) *3
310(MSOP8) *4
Storage temperature
Tstg
-65 to +125
°C
Operating temperature
Topr
-40 to +85
°C
Terminal voltage
-
-0.3 to VCC+0.3
V
*1 Reduced by 8.0mW for each increase in Ta of 1°C over 25°C. *2 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C. *3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. *4 Reduced by 3.1mW for each increase in Ta of 1°C over 25°C.
BR24L04FV-W Features
1) 512 registers * 8 bits serial architecture. 2) Single power supply (1.8V to 5.5V). 3) Two wire serial interface. 4) Self-timed write cycle with automatic erase. 5) 16byte Page Write mode. 6) Low power consumption. Write (5V) : 1.2mA (Typ.) Read (5V) : 0.2mA (Typ.) Standby (5V) : 0.1A (Typ.) 7) DATA security Write protect feature (WP pin). Inhibit to WRITE at low VCC. 8) Small package - - - DIP8 / SOP8 / SOP-J8 / SSOP-B8 / MSOP-8 9) High reliability EEPROM with Double-Cell structure 10) High reliability fine pattern CMOS technology. 11) Endurance : 1,000,000 erase / write cycles 12) Data retention : 40 years 13) Filtered inputs in SCL*SDA for noise suppression. 14) Initial data FFh in all address.