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AX11005, AX11015, AX11025

Table of contents:
Info of AX11005
Info of AX11015
Info of AX11025

AX11005, AX11015, AX11025 Selling Leads, Datasheet

MFG:ASIX Package Cooled:QFP D/C:07+

AX11005, AX11015, AX11025 Datasheet download

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Part Number: AX11005

MFG: ASIX

Package Cooled: QFP

D/C: 07+

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AX11005 General Description

The AX11001/AX11005, Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a System-on-Chip (SoC) solution which offers a high performance embedded micro controller and rich communication peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol stack, the AX11001/AX11005 provides very cost effective networking solution to enable simple, easy, and low cost Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial equipments, security systems, remote data collection equipments, remote control, remote monitoring, and remote management. In addition to stand-alone application, the AX11001/AX11005, with popular TCP/IP protocol suite on-chip and built-in I2C bus or SPI bus, can be used as network co-processor to offload TCP/IP protocol processing loading from system CPU in an embedded system.

AX11005 Maximum Ratings

8-bit pipelined RISC, single cycle per instruction with maximum operating frequency of 100MHz (100 MIPS)
100% software compatible with standard 8051/80390
2 GPIO ports of 8 bits each
2 external interrupt sources with 2 priority levels
Supports power management unit, programmable watchdog timer and 3 16-bit timer/counters
Debug port for connecting to In-Circuit Emulation (ICE) adaptor
5 channels of Programmable Counter Array (PCA)

On-chip Program and Data Memory

Embeds 512KB Flash memory without bank select and 16KB SRAM for program code mirroring
Supports initial Flash memory programming via UART or ICE adaptor, the so-called In System Programming (ISP)
Supports reprogrammable boot code and In Application Programming (IAP) to update run-time firmware or boot code through Ethernet or UART (US Patent Pending)
Embeds 32KB SRAM for data memory

Buffer Management

Embeds DMA engine and memory arbiter. Support 3 DMA channels for high performance data movement needed for network protocol stack processing

On-chip 10/100M Fast Ethernet MAC and PHY

Integrates IEEE 802.3 10BASE-T/100BASE-TX compatible Fast Ethernet MAC and PHY with dedicated 12KB SRAM for Ethernet packet buffering. Support full-duplex and half-duplex operations
Supports twisted pair crossover detection and auto-correction (Auto-MDIX)
Supports wakeup via Link-up, Magic packet, Wakeup frame or external input pin

TCP/IP

Build in TCP/IP accelerator in hardware to improve network transfer throughput. Support IP/TCP/UDP/ICMP/IGMP checksum and ARP in hardware
Supports TCP, UDP, ICMP, IPv4, DHCP, BOOTP, ARP, DNS, SMTP, SNTP, uPNP, PPPoE and HTTP in software

Communication Interface

3 UART interface (with 1 supporting 921.6Kbps and Modem control)
I²C interface (master and slave mode)
SPI/Micro wire interface (3 masters or 1 slave mode)
1-Wire controller interface (master mode)
10/100 Ethernet PHY interface

Supports network boot over Ethernet using BOOTP and TFTP
Integrates on-chip 3.3V to 1.8V voltage regulator and require single power supply of 3.3V only
Integrates on-chip oscillator and PLL. Require only one 25MHz crystal to operate
Integrates on-chip power-on reset circuit
80-pin LQFP or 80-pin TFBGA RoHS package
Operating temperature: 0°C to 70°C or -40°C to 85°C

AX11005 Features

MCU
8-bit pipelined RISC, single cycle per
instruction with maximum operating
frequency of 100Mhz (100 MIPS)
100% software compatible with standard
8051/80390
2 GPIO ports of 8 bits each
2 external interrupt sources with 2 priority
levels
Support power management unit,
programmable watchdog timer, and 3 16-bit
timer/counters
Debug port for connecting to In-Circuit
Emulation (ICE) adaptor
5 channels of Programmable Counter Array
(PCA)
On-chip Program and Data Memory
Embed 128K (AX11001) or 512KB
(AX11005) Flash memory without bank
select, and 16KB SRAM for program code
mirroring
Support initial Flash memory programming
via UART or ICE adaptor, the so-called In
System Programming (ISP)
Support run-time firmware or driver update
through Ethernet or UART, the so-called In
Application Programming (IAP)
Embed 32KB SRAM for data memory
Buffer Management
Embed DMA engine and memory arbiter.
Support 3 DMA channels for high
performance data movement needed for
network protocol stack processing
On-chip 10/100M Fast Ethernet MAC and PHY
Integrate IEEE 802.3 10BASE-T/100BASE-TX
compatible Fast Ethernet MAC and PHY with
dedicated 12KB SRAM for Ethernet packet
buffering. Support full-duplex and half-duplex
operations
Support twisted pair crossover detection and
auto-correction (Auto-MDIX)
Support wakeup via Link-up, Magic packet,
Wakeup frame, external input pin, or UART
TCP/IP
Build in TCP/IP accelerator in hardware to
improve network transfer throughput. Support
IP/TCP/UDP/ICMP/IGMP checksum and
ARP in hardware
Support TCP, UDP, ICMP, IGMP, IPv4,
DHCP, BOOTP, ARP, and HTTP in software
Communication Interface
3 UART interface (with 1 supporting
921.6Kbps and Modem control)
1 I2C interface (master and slave mode)
SPI/Micro wire interface (3 masters or 1 slave
mode)
1 1-Wire controller interface (master mode)
10/100 Ethernet PHY interface
Support network boot over Ethernet using BOOTP
and TFTP
Integrate on-chip 3.3V to 1.8V voltage regulator and
require single power supply of 3.3V only
Integrate on-chip oscillator and PLL. Require only
one 25Mhz crystal to operate
Integrate on-chip power-on reset circuit
80-pin LQFP or 80-pin TFBGA RoHS package
Operating temperature: 0 to 70°C or -40 to 85°C

AX11005 Typical Application

The AX11001/AX11005, with on-chip high performance RISC CPU, built-in TCP/IP protocol suite, and rich communication peripherals supported, provides a very low cost yet very high performance SoC solution to enable easy and simple LAN or Internet access capability to almost every application needs in the Internet era. The AX11001/AX11005 is targeted for home appliances, factory/building automation, industrial equipments, security systems, remote control/monitoring/management, and streaming media applications such as network camera/remote surveillance, hardware TCP/IP offload engine, audio over Internet, automatic meter reading, vending system/POS, environment monitoring or network sensor, networked UPS, serial to Ethernet adaptor and Ethernet to ZigBee bridge, etc.

AX11005 Connection Diagram

AX11015 General Description

The AX11015, Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a System-on-Chip (SoC) solution which offers a high performance embedded micro controller and rich communication peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol stack, the AX11015 provides very cost effective networking solution to enable simple, easy and low cost Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial equipments, security systems, remote data collection equipments, remote control, remote monitoring and remote management. In addition to stand-alone application, the AX11015, with popular TCP/IP protocol suite on-chip and built-in local bus host interface, I²C bus, or SPI bus, can be used as network co-processor to offload TCP/IP protocol processing loading from system CPU in an embedded system

AX11015 Maximum Ratings

8-bit pipelined RISC, single cycle per instruction with maximum operating frequency of 100MHz (100 MIPS)
100% software compatible with standard 8051/80390
4 GPIO ports of 8 bits each
2 external interrupt sources with 2 priority levels
Supports power management unit, programmable watchdog timer and 3 16-bit timer/counters
Debug port for connecting to In-Circuit Emulation (ICE) adaptor
5 channels of Programmable Counter Array (PCA)

On-chip Program and Data Memory

Embeds 512KB Flash memory and 16KB SRAM for program code mirroring. The external program memory can grow up to 2MB without bank select
Supports initial Flash memory programming via UART or ICE adaptor, the so-called In System Programming (ISP)
Supports reprogrammable boot code and In Application Programming (IAP) to update run-time firmware or boot code through Ethernet or UART (US Patent Pending)
Supports boot loader to shadow program code on to internal 16KB SRAM and external SRAM for high performance applications
Embeds 32KB SRAM for data memory, expandable up to 2MB via external SRAM without bank select

Buffer Management

Innovative shared memory architecture to allow external program and data memory to share the same SRAM memory chip with flexible memory space allocation
Embeds DMA engine and memory arbiter. Support 5 DMA channels for high performance data movement needed for network protocol stack processing

On-chip 10/100M Fast Ethernet MAC and PHY

Integrates IEEE 802.3 10BASE-T/100BASE-TX compatible Fast Ethernet MAC and PHY with dedicated 12KB SRAM for Ethernet packet buffering. Support full-duplex and half-duplex operations. Provide optional MII interface (for HomePNA and HomePlug)
Supports twisted pair crossover detection and auto-correction (Auto-MDIX)
Supports wakeup via Link-up, Magic packet, Wakeup frame or external input pin

TCP/IP

Builds in TCP/IP accelerator in hardware to improve network transfer throughput. Support IP/TCP/UDP/ICMP/IGMP checksum and ARP in hardware
Supports TCP, UDP, ICMP, IPv4, DHCP, BOOTP, ARP, DNS, SMTP, SNTP, uPNP, PPPoE and HTTP in software

Communication Interface

3 UART interface (with 1 supporting 921.6Kbps and Modem control)
I²C interface (master and slave mode)
Local bus host interface (master or slave mode)
SPI/Micro wire interface (3 masters or 1 slave mode)
1-Wire controller interface (master mode)
10/100 Ethernet PHY interface

Supports network boot over Ethernet using BOOTP and TFTP
Integrates on-chip 3.3V to 1.8V voltage regulator and require single power supply of 3.3V only
Integrates on-chip oscillator and PLL. Require only one 25MHz crystal to operate
Integrates on-chip power-on reset circuit
128-pin LQFP RoHS package
Operating temperature: 0°C to +70°C or -40°C to +85°C

AX11015 Connection Diagram

AX11025 General Description

The AX11025, Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a System-on-Chip (SoC) solution which offers a high performance embedded micro controller and rich communication peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol stack, the AX11025 provides very cost effective networking solution to enable simple, easy, and low cost Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial equipments, security systems, remote data collection equipments, remote control, remote monitoring, and remote management.

AX11025 Maximum Ratings

8-bit pipelined RISC, single cycle per instruction with maximum operating frequency of 100MHz (100 MIPS)
100% software compatible with standard 8051/80390
4 GPIO ports of 8 bits each
2 external interrupt sources with 2 priority levels
Supports power management unit, programmable watchdog timer and 3 16-bit timer/counters
Debug port for connecting to In-Circuit Emulation (ICE) adaptor
5 channels of Programmable Counter Array (PCA)

On-chip Program and Data Memory

Embeds 512KB Flash memory and 16KB SRAM for program code mirroring. The external program memory can grow up to 2MB without bank select
Supports initial Flash memory programming via UART or ICE adaptor, the so-called In System Programming (ISP)
Supports reprogrammable boot code and In Application Programming (IAP) to update run-time firmware or boot code through Ethernet or UART (US Patent Pending)
Supports boot loader to shadow program code on to internal 16KB SRAM and external SRAM for high performance applications
Embeds 32KB SRAM for data memory, expandable up to 2MB via external SRAM without bank select

Buffer Management

Innovative shared memory architecture to allow external program and data memory to share the same SRAM memory chip with flexible memory space allocation
Embeds DMA engine and memory arbiter. Support 3 DMA channels for high performance data movement needed for network protocol stack processing

On-chip 10/100M Fast Ethernet MAC and PHY

Integrates IEEE 802.3 10BASE-T/100BASE-TX compatible Fast Ethernet MAC and PHY with dedicated 12KB SRAM for Ethernet packet buffering. Support full-duplex and half-duplex operations. Provide optional MII interface (for HomePNA and HomePlug)
Supports twisted pair crossover detection and auto-correction (HP Auto-MDIX)
Supports wakeup via Link-up, Magic packet, Wakeup frame or external input pin

TCP/IP

Build in TCP/IP accelerator in hardware to improve network transfer throughput. Support IP/TCP/UDP/ICMP/IGMP checksum and ARP in hardware
Supports TCP, UDP, ICMP, IPv4, DHCP, BOOTP, ARP, DNS, SMTP, SNTP, uPNP, PPPoE and HTTP in software

Communication Interface

3 UART interface (with 1 supporting 921.6Kbps and Modem control)
SPI/Micro wire interface (3 masters or 1 slave mode)
I²C interface (master and slave mode)
1-Wire controller interface (master mode)
1 CAN 2.0 controller interface
10/100 Ethernet PHY interface

Supports network boot over Ethernet using BOOTP and TFTP
Integrates on-chip 3.3V to 1.8V voltage regulator and require single power supply of 3.3V only
Integrates on-chip oscillator and PLL. Require only one 25MHz crystal to operate
Integrates on-chip power-on reset circuit
128-pin LQFP RoHS package
Operating temperature: -40°C to 85°C

AX11025 Features

MCU
8-bit pipelined RISC, single cycle per
instruction with maximum operating
frequency of 100Mhz (100 MIPS)
100% software compatible with standard
8051/80390
4 GPIO ports of 8 bits each
2 external interrupt sources with 2 priority
levels
Support power management unit,
programmable watchdog timer, and 3 16-bit
timer/counters
Debug port for connecting to In-Circuit
Emulation (ICE) adaptor
5 channels of Programmable Counter Array
(PCA)
On-chip Program and Data Memory
Embed 512KB Flash memory, and 16KB
SRAM for program code mirroring. The
external program memory can grow up to
2MB without bank select
Support initial Flash memory programming
via UART or ICE adaptor, the so-called In
System Programming (ISP)
Support run-time firmware or driver update
through Ethernet or UART, the so-called In
Application Programming (IAP)
Support boot loader to shadow program code
on to internal 16KB SRAM and external
SRAM for high performance applications
Embed 32KB SRAM for data memory,
expandable up to 2MB via external SRAM
without bank select
Buffer Management
Innovative shared memory architecture to
allow external program and data memory to
share the same SRAM memory chip with
flexible memory space allocation
Embed DMA engine and memory arbiter.
Support 3 DMA channels for high
performance data movement needed for
network protocol stack processing
On-chip 10/100M Fast Ethernet MAC and PHY
Integrate IEEE 802.3 10BASE-T/100BASE-TX
compatible Fast Ethernet MAC and PHY with
dedicated 12KB SRAM for Ethernet packet
buffering. Support full-duplex and half-duplex
operations. Provide optional MII interface (for
HomePNA and HomePlug)
Support twisted pair crossover detection and
auto-correction (HP Auto-MDIX)
Support wakeup via Link-up, Magic packet,
Wakeup frame or external input pin
TCP/IP
Build in TCP/IP accelerator in hardware to
improve network transfer throughput. Support
IP/TCP/UDP/ICMP/IGMP checksum and
ARP in hardware
Support TCP, UDP, ICMP, IGMP, IPv4,
DHCP, BOOTP, ARP, and HTTP in software
Communication Interface
3 UART interface (with 1 supporting
921.6Kbps and Modem control)
1 I2C interface (master and slave mode)
SPI/Micro wire interface (3 masters or 1 slave
mode)
1 1-Wire controller interface (master mode)
1 CAN 2.0 controller interface
10/100 Ethernet PHY interface
Support network boot over Ethernet using BOOTP
and TFTP
Integrate on-chip 3.3V to 1.8V voltage regulator and
require single power supply of 3.3V only
Integrate on-chip oscillator and PLL. Require only
one 25Mhz crystal to operate
Integrate on-chip power-on reset circuit
128-pin LQFP RoHS package
Operating temperature: -40 to 85°C

AX11025 Typical Application

The AX11025, with on-chip high performance RISC CPU, built-in TCP/IP protocol suite, and rich communication peripherals supported, provides a very low cost yet very high performance SoC solution to enable easy and simple LAN or Internet access capability to almost every application needs in the Internet era. The AX11025 is targeted for home appliances, factory/building automation, industrial equipments, security systems, remote control/monitoring/management, and streaming media applications such as network camera/remote surveillance, hardware TCP/IP offload engine, audio over Internet, automatic meter reading, vending system/POS, environment monitoring or network sensor, networked UPS, serial to Ethernet adaptor, CAN2.0 (Control Area Network) to Ethernet
adaptor and Ethernet to ZigBee bridge, etc.

AX11025 Connection Diagram

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