AT8985P, AT8985PC, AT8985PC(A4) Selling Leads, Datasheet
MFG:ATAN Package Cooled:QFP D/C:02+
AT8985P, AT8985PC, AT8985PC(A4) Datasheet download
Part Number: AT8985P
MFG: ATAN
Package Cooled: QFP
D/C: 02+
MFG:ATAN Package Cooled:QFP D/C:02+
AT8985P, AT8985PC, AT8985PC(A4) Datasheet download
MFG: ATAN
Package Cooled: QFP
D/C: 02+
Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
TOP
PDF/DataSheet Download
Datasheet: at8985p
File Size: 281834 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: AT8
File Size: 55024 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: AT8
File Size: 55024 KB
Manufacturer:
Download : Click here to Download
The AT8985P is a high performance, low cost, highly integration (Controller, PHY and Memory) five-port 10/100 Mbps TX/FX plus one 10/100M MAC port Ethernet switch controller with all ports supporting 10/100 Mbps Full/Half duplex switch function. The AT8985P is intended for applications to stand alone bridge for low cost SOHO market such as 5Port switch or plus one CPU Router. AT8985P provide most advance function such as: 802.1p(Q.O.S.),802.1q(VLAN), Port MAC address Locking, TP Auto MDIX , 25M Crystal & Extra sixth MII port function to meet customer request on Switch demand.
The AT8985P also supports Back-Pressure in Half-Duplex mode and 802.3x Flow Control Pause packet in Full-Duplex mode to prevent packet lost when buffer full. When Back Pressure is enabled, and there is no receive buffer available for the incoming packet, the AT8985P will issue a JAM pattern on the receiving port in Half Duplex mode and transmit the 802.3x Pause packet back to receiving end in Full Duplex mode.
The built-in 1Mbit SRAM used for packet buffer and address learning table is divided into 256 bytes/block to achieve the optimized memory utilization through complicated link list on packets with various lengths.
AT8985P also supports Port-Base, VLAN and IP TOS field checking for priority mapping. User can be easy to set as different priority mode in individual port, through a small low-cost micro controller to initialize or on-the-fly to configure.
Each output port supports four queues in the way of fixed 8:4:2:1 fairness queuing to fit the bandwidth demand on various types of packet such as Voice, Video and data. 802.1Q, Tag/Untag, and up to 16 groups of VLAN also is supported. AT8985P learn last 4 bits of VLAN ID.
An intelligent address recognition algorithm makes AT8985P to recognize up to 2048 different MAC addresses and enables filtering and forwarding at full wire speed.
Port MAC address Locking function is also supported by AT8985P for customer used on Building Internet access to prevent multiple users share one port traffic.
Symbol |
Parameter |
Rating |
Units |
VCC |
Power Supply |
-0.3 to 3.63 |
V |
Vcca2 |
TX line driver |
-0.3 to 2.75 |
V |
Vccpll |
PLL voltage |
-0.3 to 2.75 |
V |
Vccik |
Digital core voltage |
-0.3 to 2.75 |
V |
VIN |
Input Voltage |
-0.3 to VCC + 0.3 |
V |
Vout |
Output Voltage |
-0.3 to VCC + 0.3 |
V |
TSTG |
Storage Temperature |
-55 to 155 |
°C |
PD |
Power Dissipation |
3 |
W |
ESD |
ESD Rating |
2KV |
V |