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APA075-TQG100I, APA075-TQG144I, APA1000

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Info of APA075-TQG100I
Info of APA075-TQG144I
Info of APA1000

APA075-TQG100I, APA075-TQG144I, APA1000 Selling Leads, Datasheet

MFG:ACTEL Package Cooled:QFP D/C:10

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APA075-TQG100I, APA075-TQG144I, APA1000 Datasheet download

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Part Number: APA075-TQG100I

MFG: ACTEL

Package Cooled: QFP

D/C: 10

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APA1000 General Description

The ProASIC^PLUS family of devices, Actel's second generation Flash FPGAs, offers enhanced performance over Actel's ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASIC^PLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). The family offers up to 1 million system gates, supported with up to 198kbits of 2-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance.

Advantages to the designer extend beyond performance. Unlike SRAM-based FPGAs, four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be live at power-up. No external Boot PROM is required to support device programming. While on-board security mechanisms prevent all access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades. The device's architecture mitigates the complexity of ASIC migration at higher user volume. This makes ProASICPLUS a cost-effective solution for applications in the networking, communications, computing, and avionics markets.

The ProASIC^PLUS family achieves its nonvolatility and reprogrammability through an advanced Flash-based 0.22m LVCMOS process with four-layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. This results in predictable performance fully compatible with gate arrays.

The ProASIC^PLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-Tiles.. Each tile can be configured as a flip-flop, latch, or 3-input/1-output logic function by programming the appropriate Flash switches. The combination of fine granularity, flexible routing resources, and abundant Flash switches allow 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a 4-level routing hierarchy.

Embedded 2-port SRAM blocks with built-in FIFO/RAM control logic can have user-defined depth and width. Users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking.

The unique clock conditioning circuitry in each device includes two clock conditioning blocks. Each block provides a PLL core, delay lines, phase shifts (0°, 90°, 180°, 270°), and clock multipliers/dividers, as well as the circuitry needed to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers, which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit also delays or advances the incoming reference clock up to 8 ns (in increments of 0.25 ns). The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high speed clock and data inputs.

To support customer needs for more comprehensive, lower cost board-level testing, Actel's ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. For more information concerning the Flash FPGA implementation, please refer to the "Boundary Scan (JTAG)" section on page 13.

ProASIC^PLUS devices are available in a variety of high-performance plastic packages. Those packages and the performance features discussed above are described in more detail in the following sections.

APA1000 Maximum Ratings

Parameter	Condition	Minimum	Maximum	Units
Supply Voltage Core (V_DD )		0.3	3.0	V
Supply Voltage I/O Ring (V_DDP)		0.3	4.0	V
DC Input Voltage		0.3	V_DDP + 0.3	V
PCI DC Input Voltage		-1.0	V_DDP + 1.0	V
PCI DC Input Clamp Current (absolute)	V_IN < 1 or VIN= V_DDP + 1V	10		mA
LVPECL Input Voltage		0.3	V_DDP + 0.5	V
GND		0	0	V

APA1000 Features

High Capacity
   • 75,000 to 1 million System Gates
   • 27k to 198kbits of Two-Port SRAM
   • 66 to 712 User I/Os
Reprogrammable Flash Technology
   • 0.22 4LM Flash-based CMOS Process
   • Live at Power-Up, Single-Chip Solution
   • No Configuration Device Required
   • Retains Programmed Design during Power-Down/ Power-Up Cycles
Performance
   • 3.3V, 32-bit PCI (up to 50 MHz)
   • Two Integrated PLLs
   • External System Performance up to 150 MHz
Secure Programming
   • The Industry's Most Effective Security Key (FlashLock^TM) Prevents Read Back of Programming Bitstream
Low Power
   • Low Impedance Flash Switches
   • Segmented Hierarchical Routing Structure
   • Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells
High Performance Routing Hierarchy
   • Ultra-Fast Local and Long-Line Network
   • High Speed Very Long-Line Network
   • High Performance, Low Skew, Splittable Global Network
   • 100% Routability and Utilization
I/O
   • Schmitt-Trigger Option on Every Input
   • Mixed 2.5V/3.3V Support with IndividuallypiusSelectable
Voltage and Slew Rate
   • Bidirectional Global I/Os
   • Compliance with PCI Specification Revision 2.2
   • Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
   • Pin Compatible Packages across ProASICPLUS Family
Unique Clock Conditioning Circuitry
   • PLL with Flexible Phase, Multiply/Divide and Delay Capabilities
   • Internal and/or External Dynamic PLL Configuration
   • Two LVPECL Differential Pairs for Clock or Data Inputs
Standard FPGA and ASIC Design Flow
   • Flexibility with Choice of Industry-Standard Frontend Tools
   • Efficient Design through Frontend Timing and Gate Optimization
ISP Support
   • In-System Programming (ISP) via JTAG Port
SRAMs and FIFOs
   • ACTgen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks
   • 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical)

APA1000 Connection Diagram

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