AM79C972, AM79C9728KC, AM79C972AKI Selling Leads, Datasheet
MFG:IC Package Cooled:QFP D/C:AM
AM79C972, AM79C9728KC, AM79C972AKI Datasheet download
Part Number: AM79C972
MFG: IC
Package Cooled: QFP
D/C: AM
AM79C972, AM79C9728KC, AM79C972AKI
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Info of AM79C972
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About AM79C972
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Datasheet: AM79C972
File Size: 1543370 KB
Manufacturer: AMD [Advanced Micro Devices]
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AM79C972 General Description
The Am79C972 PCnet-FAST+ controller is a highlyintegrated 32-bit full-duplex, 10/100-Megabit per second (Mbps) Ethernet controller solution, designed to address high-performance system application requirements. It is a flexible bus mastering device that can be used in any application, including network-ready PCs and bridge/router designs. The bus master architecture provides high data throughput and low CPU and system bus utilization. The Am79C972 controller is fabricated with advanced low-power 3.3-V CMOS process to provide low operating current for power sensitive applications.
The Am79C972 PCnet-FAST+ controller also has several enhancements over its predecessor, the Am79C971 PCnet-FAST device. In addition to integrating the SRAM on chip, it further reduces system implementation cost by the addition of a new EEPROM programmable pin (PHY_RST), an internal oscillator circuit eliminating the need for an external crystal, and the integration of the PAL function needed for Magic Packet application. The PHY_RST pin is implemented to reset the external PHY without increasing the load to the PCI bus and to block RST to the PHY when PG input is LOW.
The 32-bit multiplexed bus interface unit provides a direct interface to the PCI local bus, simplifying the design of an Ethernet node in a PC system. The Am79C972 PCnet-FAST+ controller provides the complete interface to an Expansion ROM or Flash device allowing add-on card designs with only a single load per PCI bus interface pin. With its built-in support for both little and big endian byte alignment, this controller also addresses non-PC applications. The Am79C972 controller's advanced CMOS design allows the bus interface to be connected to either a +5-V or a +3.3-V signaling environment. A compliant IEEE 1149.1 JTAG test interface for board-level testing is also provided, as well as a NAND tree test structure for those systems that cannot support the JTAG interface.
The Am79C972 PCnet-FAST+ controller is also compliant with the PC97, PC98, and Net PC specifications. It includes the full implementation of the Microsoft OnNow and ACPI specifications, which are backward compatible with the Magic Packet technology, and is compliant with the PCI Bus Power Management Interface Specification by supporting the four power management states (D0, D1, D2, and D3), the optional PME pin, and the necessary configuration and data registers.
The Am79C972 PCnet-FAST+ controller is ideally suited for Network PC (Net PC), motherboard, network interface card (NIC), and embedded designs. It is available in a 160-pin Plastic Quad Flat Pack (PQFP) package and also in a 176-pin Thin Quad Flat Pack (TQFP) package for form factor sensitive designs.
The Am79C972 PCnet-FAST+ controller is a complete Ethernet node integrated into a single VLSI device. It contains a bus interface unit, a Direct Memory Access (DMA) Buffer Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)-compliant Media Access Controller (MAC), a large Transmit FIFO and a large Receive FIFO, and an IEEE 802.3-compliant MII. Both IEEE 802.3 compliant full-duplex and half-duplex operations are supported on the MII and GPSI interfaces. 10/100 Mbps operation is supported through the MII.
The Am79C972 PCnet-FAST+ controller also has several enhancements over its predecessor, the Am79C971 PCnet-FAST device. In addition to integrating the SRAM on chip, it further reduces system implementation cost by the addition of a new EEPROM programmable pin (PHY_RST), an internal oscillator circuit eliminating the need for an external crystal, and the integration of the PAL function needed for Magic Packet application. The PHY_RST pin is implemented to reset the external PHY without increasing the load to the PCI bus and to block RST to the PHY when PG input is LOW.
The 32-bit multiplexed bus interface unit provides a direct interface to the PCI local bus, simplifying the design of an Ethernet node in a PC system. The Am79C972 PCnet-FAST+ controller provides the complete interface to an Expansion ROM or Flash device allowing add-on card designs with only a single load per PCI bus interface pin. With its built-in support for both little and big endian byte alignment, this controller also addresses non-PC applications. The Am79C972 controller's advanced CMOS design allows the bus interface to be connected to either a +5-V or a +3.3-V signaling environment. A compliant IEEE 1149.1 JTAG test interface for board-level testing is also provided, as well as a NAND tree test structure for those systems that cannot support the JTAG interface.
The Am79C972 PCnet-FAST+ controller is also compliant with the PC97, PC98, and Net PC specifications. It includes the full implementation of the Microsoft OnNow and ACPI specifications, which are backward compatible with the Magic Packet technology, and is compliant with the PCI Bus Power Management Interface Specification by supporting the four power management states (D0, D1, D2, and D3), the optional PME pin, and the necessary configuration and data registers.
The Am79C972 PCnet-FAST+ controller is ideally suited for Network PC (Net PC), motherboard, network interface card (NIC), and embedded designs. It is available in a 160-pin Plastic Quad Flat Pack (PQFP) package and also in a 176-pin Thin Quad Flat Pack (TQFP) package for form factor sensitive designs.
The Am79C972 PCnet-FAST+ controller is a complete Ethernet node integrated into a single VLSI device. It contains a bus interface unit, a Direct Memory Access (DMA) Buffer Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)-compliant Media Access Controller (MAC), a large Transmit FIFO and a large Receive FIFO, and an IEEE 802.3-compliant MII. Both IEEE 802.3 compliant full-duplex and half-duplex operations are supported on the MII and GPSI interfaces. 10/100 Mbps operation is supported through the MII.
AM79C972 Features
*Integrated Fast Ethernet controller for the Peripheral Component Interconnect (PCI) bus
- 32-bit glueless PCI host interface
- Supports PCI clock frequency from DC to 33 MHz independent of network clock
- Supports network operation with PCI clock from 15 MHz to 33 MHz
- High performance bus mastering architecture with integrated Direct Memory Access (DMA) Buffer Management Unit for low CPU and bus utilization
- PCI specification revision 2.1 compliant
- Supports PCI Subsystem/Subvendor ID/Vendor ID programming through the EEPROM interface
- Supports both PCI 3.3-V and 5.0-V signaling environments
- Plug and Play compatible
- Supports an unlimited PCI burst length
- Big endian and little endian byte alignments supported
- Implements optional PCI power management event (PME) pin
* Media Independent Interface (MII) for connecting external 10/100 megabit per second (Mbps) transceivers
- IEEE 802.3-compliant MII
- Intelligent Auto-Poll™ external PHY status monitor and interrupt
- Supports both auto-negotiable and non auto-negotiable external PHYs
- Supports 10BASE-T, 100BASE-TX/FX, 100BASE-T4, and 100BASE-T2 IEEE 802.3-compliant MII PHYs at full- or half-duplex
*Supports General Purpose Serial Interface (GPSI) with receive frame tagging support for internetworking applications
*Full-duplex operation supported in MII and GPSI ports with independent Transmit (TX) and Receive (RX) channels
*Supports PC97, PC98, and Net PC requirements
- Implements full OnNow features including pattern matching and link status wake-up
- Implements Magic Packet mode
- Magic Packet mode and the physical address loaded from EEPROM at power up without requiring PCI clock
- Supports PCI Bus Power Management Interface Specification Version 1.0
- Supports Advanced Configuration and Power Interface (ACPI) Specification Version 1.0
- Supports Network Device Class Power Management Specification Version 1.0
*Large independent internal TX and RX FIFOs
- Programmable FIFO watermarks for both transmit and receive operations
- Receive frame queuing for high latency PCI bus host operation
- Programmable allocation of buffer space between transmit and receive queues
*Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue Book Ethernet standards
*EEPROM interface supports jumperless design and provides through-chip programming
- Supports full programmability of half-/fullduplex operation for external 10/100 Mbps PHYs through EEPROM mapping
- Programmable PHY reset output pin capable of resetting external PHY without needing buffering
*Integrated oscillator circuit eliminates need for external crystal
*Extensive programmable LED status support
*Support for operation in industrial temperature range (-40°C to +85°C)
- 32-bit glueless PCI host interface
- Supports PCI clock frequency from DC to 33 MHz independent of network clock
- Supports network operation with PCI clock from 15 MHz to 33 MHz
- High performance bus mastering architecture with integrated Direct Memory Access (DMA) Buffer Management Unit for low CPU and bus utilization
- PCI specification revision 2.1 compliant
- Supports PCI Subsystem/Subvendor ID/Vendor ID programming through the EEPROM interface
- Supports both PCI 3.3-V and 5.0-V signaling environments
- Plug and Play compatible
- Supports an unlimited PCI burst length
- Big endian and little endian byte alignments supported
- Implements optional PCI power management event (PME) pin
* Media Independent Interface (MII) for connecting external 10/100 megabit per second (Mbps) transceivers
- IEEE 802.3-compliant MII
- Intelligent Auto-Poll™ external PHY status monitor and interrupt
- Supports both auto-negotiable and non auto-negotiable external PHYs
- Supports 10BASE-T, 100BASE-TX/FX, 100BASE-T4, and 100BASE-T2 IEEE 802.3-compliant MII PHYs at full- or half-duplex
*Supports General Purpose Serial Interface (GPSI) with receive frame tagging support for internetworking applications
*Full-duplex operation supported in MII and GPSI ports with independent Transmit (TX) and Receive (RX) channels
*Supports PC97, PC98, and Net PC requirements
- Implements full OnNow features including pattern matching and link status wake-up
- Implements Magic Packet mode
- Magic Packet mode and the physical address loaded from EEPROM at power up without requiring PCI clock
- Supports PCI Bus Power Management Interface Specification Version 1.0
- Supports Advanced Configuration and Power Interface (ACPI) Specification Version 1.0
- Supports Network Device Class Power Management Specification Version 1.0
*Large independent internal TX and RX FIFOs
- Programmable FIFO watermarks for both transmit and receive operations
- Receive frame queuing for high latency PCI bus host operation
- Programmable allocation of buffer space between transmit and receive queues
*Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue Book Ethernet standards
*EEPROM interface supports jumperless design and provides through-chip programming
- Supports full programmability of half-/fullduplex operation for external 10/100 Mbps PHYs through EEPROM mapping
- Programmable PHY reset output pin capable of resetting external PHY without needing buffering
*Integrated oscillator circuit eliminates need for external crystal
*Extensive programmable LED status support
*Support for operation in industrial temperature range (-40°C to +85°C)
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