80J101, 80KSBR200, 80KSW0002AR Selling Leads, Datasheet
Package Cooled:TO3PL D/C:03+
80J101, 80KSBR200, 80KSW0002AR Datasheet download
Part Number: 80J101
MFG: --
Package Cooled: TO3PL
D/C: 03+
80J101, 80KSBR200, 80KSW0002AR
- Table of contents:
Info of 80J101
Info of 80KSBR200
Info of 80KSW0002AR
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Datasheet:
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Manufacturer:
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80KSBR200 General Description
The IDT80KSBR200 is a high speed Serial Buffer (SerB) that can connect to any Serial RapidIO compliant interface. This device is built to work with any sRIO device and especially with the IDT Pre-Processing Switch (PPS), IDT70K200. The SerB performs buffering and off-loading of data as well as buffer-delay of data samples in various environments. This device primarily acts as an master in which the SerB bursts data to a programmed memory location once some criteria have been meet. This combination of storage and flexibility make it the perfect buffering solution for sRIO systems.
80KSBR200 Maximum Ratings
| Symbol | Rating | Commercial & Industrial | Unit |
| VTERM (VDD3) VTERM(2) (VDD3-supplied interfaces) VTERM (VDD) VTERM(2) (VDD-supplied interfaces) VTERM (VDDS) VTERM(2) (VDDS-supplied interfaces) VTERM (VDDA) VTERM(2) (VDDA-supplied interfaces) TBIAS(3) TSTG TJN IOUT (For VDD3 = 3.3V) IOUT (For VDD3 = 2.5V) |
VDD3 Terminal Voltage with Respect to GND Input or I/O Terminal Voltage with Respect to GND VDD Terminal Voltage with Respect to GND Input or I/O Terminal Voltage with Respect to GND VDDS Terminal Voltage with Respect to GNDS Input or I/O Terminal Voltage with Respect to GNDS VDDA Terminal Voltage with Respect to GNDS Input or I/O Terminal Voltage with Respect to GNDS Temperature Under Bias Storage Temperature Junction Temperature DC Output Current DC Output Current |
-0.5 to 3.6 -0.3 to VDD3+0.3 -0.5 to 1.5 -0.3 to VDD+0.3 -0.5 to 1.5 -0.3 to VDDS+0.3 -0.5 to 1.5 -0.3 to VDDA+0.3 -55 to +125 -65 to +150 +150 30 30 |
V V V V V V V V C C C mA mA |
Note:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed its corresponding supply voltage during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions.
80KSBR200 Features
Serial RapidIO Port
Interface - sRIO
One four-lane (4x) link, configurable to one-lane (1x) link
Port Speeds selectable: 3.125 Gbps, 2.5 Gbps, or 1.25 Gbps
Short haul or long haul reach for each PHY speed
Support 8-bit and 16-bit deviceID
Error management supports standard
sRIO version 1.3
Class 1+ End Point Device
10 Gbps Throughput
18Mbit Internal Density
Programmable Target Address
Packet Tally Indicator
Packet Interval Timer
Replace Missing Packet
Optional External QDR SRAM Available
Up to 72Mbit external QDR SRAM
QDR SRAM, 200 MHz; (18M, 36M, 72M)
Seamless Integration of Internal and External Memory
Internal and external memory functions as a single buffer
Single Port Buffering
Status Flags for Combined Internal/External Memories
Full, Empty, Partially Empty, Partially Full
Direct or polled operation of flag status bus
Optional Watermark
Serial Buffer can Either Send a Flag or Transmit Data at a Specific Packet Count
Interface - I2C Interface Port
One I2C port for maintenance and error reporting
Interface - JTAG Interface
JTAG Functionality for boundary scan and programming
High-Speed CMOS Technology
1.2V Core operation with 3.3/2.5V JTAG interface
Package: 484-pin Plastic Ball Grid Array
23mm x 23mm, 1.0mm ball pitch
Interface - sRIO
One four-lane (4x) link, configurable to one-lane (1x) link
Port Speeds selectable: 3.125 Gbps, 2.5 Gbps, or 1.25 Gbps
Short haul or long haul reach for each PHY speed
Support 8-bit and 16-bit deviceID
Error management supports standard
sRIO version 1.3
Class 1+ End Point Device
10 Gbps Throughput
18Mbit Internal Density
Programmable Target Address
Packet Tally Indicator
Packet Interval Timer
Replace Missing Packet
Optional External QDR SRAM Available
Up to 72Mbit external QDR SRAM
QDR SRAM, 200 MHz; (18M, 36M, 72M)
Seamless Integration of Internal and External Memory
Internal and external memory functions as a single buffer
Single Port Buffering
Status Flags for Combined Internal/External Memories
Full, Empty, Partially Empty, Partially Full
Direct or polled operation of flag status bus
Optional Watermark
Serial Buffer can Either Send a Flag or Transmit Data at a Specific Packet Count
Interface - I2C Interface Port
One I2C port for maintenance and error reporting
Interface - JTAG Interface
JTAG Functionality for boundary scan and programming
High-Speed CMOS Technology
1.2V Core operation with 3.3/2.5V JTAG interface
Package: 484-pin Plastic Ball Grid Array
23mm x 23mm, 1.0mm ball pitch
80KSBR200 Typical Application
The SerB has the ability to act as a simple master.
The SerB's application with the PPS will be to broadcast data. It must be a master to perform a broadcast,
even if the data is requested.
The SerB has the ability to initiate writes. Mainly to prevent overflow and to perform broadcasts when waterlevel is reached (timed event). This avoids requiring the DSP to increase congestion by requesting data and controlling the SerB.
The SerB will typically perform SWRITEs.
The target address(s) generated by the SerB is programmable.
The packets are stored in the format they come in and are rebroadcast with simple changes to the headers
The DSPs have the ability to read the SerB registers through the PPS.
The DSP may send a maintenance read/write packets to the SerB requesting register information.
The SerB's application with the PPS will be to broadcast data. It must be a master to perform a broadcast,
even if the data is requested.
The SerB has the ability to initiate writes. Mainly to prevent overflow and to perform broadcasts when waterlevel is reached (timed event). This avoids requiring the DSP to increase congestion by requesting data and controlling the SerB.
The SerB will typically perform SWRITEs.
The target address(s) generated by the SerB is programmable.
The packets are stored in the format they come in and are rebroadcast with simple changes to the headers
The DSPs have the ability to read the SerB registers through the PPS.
The DSP may send a maintenance read/write packets to the SerB requesting register information.
80KSW0002AR General Description
Central Packet Switch CPS-16
80KSW0002AR Maximum Ratings
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