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5V9351PFGI, 5V9351PFGI8, 5V9885CPFGI

Table of contents:
Info of 5V9351PFGI
Info of 5V9351PFGI8
Info of 5V9885CPFGI

5V9351PFGI, 5V9351PFGI8, 5V9885CPFGI Selling Leads, Datasheet

MFG:IDT D/C:07+

5V9351PFGI, 5V9351PFGI8, 5V9885CPFGI Picture

5V9351PFGI, 5V9351PFGI8, 5V9885CPFGI Datasheet download

Five Points

Part Number: 5V9351PFGI

MFG: IDT

Package Cooled:

D/C: 07+

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5V9351PFGI General Description

9 LVCMOS OUT ZBD
32-pin TQFP

5V9351PFGI Maximum Ratings

Input Frequency No. of Inputs Temperature I Output Frequency No. of Outputs Voltage 2.5V/3.3V Package TQFP 32 Speed NA Input Output Output Skew Max Prop Delay Multiply Divide Jitter cycle-to-cycle Type Output Supply Voltage (VDDO) Output Style Min. Input Frequency Core Supply Voltage (VDD) Input Style Max. Output Frequency Min. Output Frequency Max. Input Frequency Temp. Grade

5V9351PFGI8 General Description

9 LVCMOS OUT ZBD
32-pin TQFP

5V9351PFGI8 Maximum Ratings

5V9885CPFGI General Description

SPREAD SPECTRUM PROG. CLK
The IDT5V9885C is a programmable clock generator intended for high performance data communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.

The IDT5V9885C can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in-system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.

Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.

There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed.

5V9885CPFGI Maximum Ratings

Temperature I Voltage 3.3 V Package TQFP 32 Speed NA Spread Spectrum Yes VCXO No Core Supply Voltage (VDD) 3.3V Output Supply Voltage (VDDO) 3.3V No. of Outputs 6 Output Style SE Input Style Crystal Max. Output Frequency 550 Min. Output Frequency 0.0049 Max. Input Frequency 400 Min. Input Frequency 1 Temp. Grade C No. of Inputs

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