Features: `Pipeline Architecture (Single-Cycle Architecture)`Single Write/Read Burst`Self-Refresh Capability (Every 16 s)`Low-Noise, Low-Voltage Transistor-Transistor Logic (LVTTL) Interface`Power-Down Mode`Compatible With JEDEC Standards`16K RAS-Only Refresh (Total for All Banks)`4K Auto Refresh...
TMS664164: Features: `Pipeline Architecture (Single-Cycle Architecture)`Single Write/Read Burst`Self-Refresh Capability (Every 16 s)`Low-Noise, Low-Voltage Transistor-Transistor Logic (LVTTL) Interface`Power-...
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Features: `Organization 512K * 16 Bits * 2 Banks`3.3-V Power Supply (±10% Tolerance)`Two Banks for...
The TMS664164 series are 67108864-bit synchronous dynamic random-access memory (SDRAM) devices which are organized as follow:
·Four banks of 1 048 576 words with 16 bits per word
·Four banks of 2097152 words with 8 bits per word
·Four banks of 4194304 words with 4 bits per word
All inputs and outputs of the TMS664xx4 series are compatible with the LVTTL interface.
The SDRAM employs state-of-the-art technology for high-performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and to enhance use with high-speed microprocessors and caches.
The TMS664164 SDRAM is available in a 400-mil, 54-pin surface-mount thin small-outline package (TSOP)
(DGE suffix).