TMS626812

Features:

`Organization . . . 1M * 8 * 2 Banks
`3.3-V Power Supply (±10% Tolerance)
`Two Banks for On-Chip Interleaving (Gapless Accesses)
`High Bandwidth Up to 83-MHz Data Rates
`CAS Latency Programmable to 2 or 3 Cycles From Column-Address Entry
`Burst Sequence Programmable to Serial or Interleave
`Burst Length Programmable to 1, 2, 4, or 8
`Chip Select and Clock Enable for Enhanced-System Interfacing
`Cycle-by-Cycle DQ-Bus Mask Capability
`Auto-Refresh and Self-Refresh Capability
`4K Refresh (Total for Both Banks)
`High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface
`Power-Down Mode
`Compatible With JEDEC Standards
`Pipeline Architecture
`Temperature Ranges Operating, 0°C to 70°C Storage, 55°C to 150°C
`Performance Ranges:


Pinout




Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 0.5 V to 4.6 V
Supply voltage range for output drivers, VCCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.

Description

The TMS626812 is a high-speed 16777216-bit synchronous dynamic random access memory (SDRAM) device organized as two banks of 1048576 words with eight bits per word.

All inputs and outputs of the TMS626812 series are compatible with the LVTTL interface.