TMS626812B

Features: ` Organization1048576 by 8 Bits by 2 Banks` 3.3-V Power Supply (±10% Tolerance)` Two Banks for On-Chip Interleaving(Gapless Accesses)` High Bandwidth Up to 125-MHz DataRates` CAS Latency (CL) Programmable to2 or 3 Cycles From Column-Address Entry` Burst Sequence Programmable to Serial o...

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TMS626812B Picture
SeekIC No. : 004525177 Detail

TMS626812B: Features: ` Organization1048576 by 8 Bits by 2 Banks` 3.3-V Power Supply (±10% Tolerance)` Two Banks for On-Chip Interleaving(Gapless Accesses)` High Bandwidth Up to 125-MHz DataRates` CAS Latency ...

floor Price/Ceiling Price

Part Number:
TMS626812B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/11

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Product Details

Description



Features:

` Organization
1048576 by 8 Bits by 2 Banks
` 3.3-V Power Supply (±10% Tolerance)
` Two Banks for On-Chip Interleaving
(Gapless Accesses)
` High Bandwidth Up to 125-MHz Data
Rates
` CAS Latency (CL) Programmable to
2 or 3 Cycles From Column-Address Entry
` Burst Sequence Programmable to Serial or
Interleave
` Burst Length Programmable to 1, 2, 4, or 8
` Chip Select and Clock Enable for Enhanced
System Interfacing
` Cycle-by-Cycle DQ Bus Mask Capability
` Auto-Refresh and Self-Refresh Capabilities
` 4K Refresh (Total for Both Banks)
` High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
` Power-Down Mode
` Compatible With JEDEC Standards
` Pipeline Architecture
` Temperature Ranges
Operating, 0°C to 70°C
Storage, 55°C to 150°C
` Intel PC100 Compliant (-8A, -8, and
-10 Devices)
` Performance Ranges:



Pinout

  Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . 0.5 V to 4.6 V
Supply voltage range for output drivers, VCCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.




Description

The TMS626812B is a high-speed, 16777216-bit synchronous dynamic random-access memory (SDRAM) device organized as follows: ` Two banks of 1048576 words with 8 bits per word (TMS626812B) All inputs and outputs of the TMS626812B series are compatible with the LVTTL interface. The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance the use with high-speed microprocessors and caches.

The TMS626812B SDRAM is available in a 400-mil, 44-pin surface-mount thin smalloutine package (TSOP) (DGE suffix).




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