Features: • High Performance Quad PCI UART
• Universal PCI Bus Buffers - Auto-sense 3.3V or 5V Operation
• 32-bit PCI Bus 2.3 Target Signalling Compliance
• A Global Interrupt Source Register for all 4 UARTs
• Data Transfer in Byte, Word and Double-word
• Data Read/Write Burst Operation
• Each UART is independently controlled with:
16C550 Compatible 5G Register Set
64-byte Transmit and Receive FIFOs
Transmit and Receive FIFO Level Counters
Automatic RTS/CTS or DTR/DSR Flow Control
Automatic Xon/Xoff Software Flow Control
Automatic RS485 Half-duplex Control Output with Selectable Turn-around Delay
Infrared (IrDA 1.0) Data Encoder/Decoder
Programmable Data Rate with Prescaler
Up to 6.25 Mbps Serial Data Rate at 8X
• Eight Multi-Purpose Inputs/outputs
• General Purpose 16-bit Timer/Counter
• Sleep Mode with Automatic Wake-up
• EEPROM Interface for PCI Configuration
• Same package and pin-out as the XR17D158, XR17C158 and XR17C154 (20x20x1.4mm 144- TQFP)
Application• Universal Form Factor PCI Bus Add-in Card
• Remote Access Servers
• Ethernet Network to Serial Ports
• Network Management
• Factory Automation and Process Control
• Point-of-Sale Systems
• Multi-port RS-232/RS-422/RS-485 CardsPinout
SpecificationsPower Supply Range (VCC) 7 volts
Voltage at any PCI Bus Pin-0.5 to (VIO+0.5) volts
Voltage at any non-PCI Bus Pin -0.5 to 7 volts
Operating Temperature -40o to +85
Storage Temperature -65o to +150
Package Dissipation 500 mW
Thermal Resistance (20x20x1.4mm 144-TQFP) theta-ja = 42, theta-jc = 8
| CH |
4 |
| CPUInterface |
PCI Bus (2.2) |
| Data Rate@5/3.3/2.5V |
6.2/4.0/na @8X |
| Tx/RxFIFO(Bytes) |
64/64 |
| Tx/RxFIFOCtrs |
Yes |
| Tx/RxFIFOINT Trig |
Program/ Program |
| AutoRTS/CTS |
Yes |
| IrDaSup |
Yes |
| AutoRS-485 |
Yes |
| 5VTolInputs |
Yes |
| Sup V |
3.3, 5 |
| Pkgs |
LQFP-144 |
DescriptionThe XR17D1541 (D154) is a quad PCI Bus Universal Asynchronous Receiver and Transmitter (UART) with same package and pin-out as the Exar XR17D154, XR17D158 and XR17C154. The device is designed to meet today's 32-bit PCI Bus and high bandwidth requirement in communication systems. The global interrupt source register provides a complete interrupt status indication for all 4 channels to speed up interrupt parsing. Each UART is independently controlled and has its own 16C550 compatible 5G register set, transmit and receive FIFOs of 64 bytes, fully programmable transmit and receive FIFO trigger levels, transmit and receive FIFO level counters, automatic hardware flow control with programmable hysteresis, automatic software (Xon/Xoff) flow control, IrDA (Infrared Data Association) encoder/ decoder, 8 multi-purpose inputs/outputs and a 16-bit general purpose timer/counter.
NOTE: 1 Covered by U.S. Patents #5,649,122, #5,949,787
XR17D154 Data Sheet
