XR-2123A

The XR-2123A utilizes CMOS technology for power operation while providing  single 5 volt operation.The XR-2123A provides the ±7 Hz carrier capture range needed for V.22 and V.26.It is externally identical to the XR-2123.Each of these devices provide the modulator and demodulator  for  phase-shifted  keyed  modulated  signals.The devices have an on-chip digital-to-analog converter, allowing digital external programming of Bell 212A, CCfTT V.22 or V.26 functions.

The XR-2123A has the following features include:(1)single +5 volt operation;(2)low power consumption (typ. 10 mw);(3)1200 BPS Full duplex;(4)2400 BPS half duplex;(5)prograrnrnable far US or European standards (CCITT);(6)Dibit PSK (DPSK) operation;(7)cyrstal controlled;(8)synthesized sine wave modulator output;(9)adjustable modulator output amplitude;(10)input protection.The baud carrier can be seen as a amplitude modulation on the 9 kHz signal. This is filtered off using a 1200 Hz band-pass filter. The Q of this filter should be approximately 2.The phase shift through this filter is very important. At 1200 Hz, the phase of the output referenced to the input should  be -90°. After the 1200 Hz bandnass filter. the signal  is applied to a level shifter and applied to Pin 26,SYN.

The absolute maximum ratings of the XR-2123A are:(1)storage temperature:-65 to +150°C;(2)operating temperature under bias:-0 to 70°C;(3)power supply:5.5V;(4)power disspation:1.0W.Please note that wish polysilicon gate inputs, the maximum voltage rating at any pin may be reached before the absolute maximum current of the input is reached. Caution should be used.The  demodulator  uses  a  pulse  width  measuring  technique which  compares  the  pattern received on  RXS within the  window  set  by  the  baud  clock,  applied  to  the synchronizer pin, SYN  This is a coherent demodulation technique, so  no reference phase is needed. The carrier clock,CCL, is  used  to  time the widths of the received pulses.As it was shown in Figure 5, the phase changes produce a distinctive pulse  pattern. The clock frequency applied to the  carrier  clock  pin,  CCL,  is changed  for each  carrier frequency  used.The  greater  the  carrier frequency, the greater the carrier clock frequency.