XQ2V6000 Selling Leads, Price trend, XQ2V6000 DataSheet download, circuit diagram from SeekIC.com

Features: • Industry First Military Grade Platform FPGA Solution• Certified to MIL-PRF-38535 (Qualified Manufacturer Listing)• 100% Factory Tested• Guaranteed over the full military temperature range (55° C to +125° C)• Ceramic and Plastic Wire-Bond and Flip-Chip Grid...

See larger image

SeekIC No. : 004549110 Detail

XQ2V6000: Features: • Industry First Military Grade Platform FPGA Solution• Certified to MIL-PRF-38535 (Qualified Manufacturer Listing)• 100% Factory Tested• Guaranteed over the full m...

XQ2V6000 Data Sheet

Get Latest Price

Part Number:: XQ2V6000
Supply Ability:: 5000

Price Break

Qty
1~5000

Unit Price
Negotiable

Processing time
15 Days

SeekIC Buyer Protection PLUS - newly updated for 2013!

Escrow Protection.
Guaranteed refunds.
Secure payments.
Learn more >>

Month Sales

268 Transactions

Rating

evaluate (4.8 stars)

Upload time: 2024/12/21

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.

Product Details

Description

Features:

• Industry First Military Grade Platform FPGA Solution
• Certified to MIL-PRF-38535 (Qualified Manufacturer Listing)
• 100% Factory Tested
• Guaranteed over the full military temperature range (55° C to +125° C)
• Ceramic and Plastic Wire-Bond and Flip-Chip Grid Array Packages
• IP-Immersion Architecture
- Densities from 1M to 6M system gates
- 300+ MHz internal clock speed (Advance Data)
- 622+ Mb/s I/O (Advance Data)
• SelectRAM™ Memory Hierarchy
- 2.5 Mb of dual-port RAM in 18 Kbit block
SelectRAM resources
- Up to 1 Mb of distributed SelectRAM resources
• High-Performance Interfaces to External Memory
- DRAM interfaces
` SDR/DDR SDRAM
` Network FCRAM
` Reduced Latency DRAM
- SRAM interfaces
` SDR/DDR SRAM
` QDR SRAM
- CAM interfaces
• Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
• Flexible Logic Resources
- Up to 67,584 internal registers/latches with Clock Enable
- Up to 67,584 look-up tables (LUTs) or cascadable
16-bit shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and sum-of-products support
- Internal 3-state busing
• High-Performance Clock Management Circuitry
- Up to 12 DCM (Digital Clock Manager) modules
` Precise clock de-skew
` Flexible frequency synthesis
` High-resolution phase shifting
- 16 global clock multiplexer buffers
• Active Interconnect Technology
- Fourth generation segmented routing structure
- Predictable, fast routing delay, independent of fanout
• SelectIO™-Ultra Technology
- Up to 824 user I/Os
- 19 single-ended and six differential standards
- Programmable sink current (2 mA to 24 mA) per I/O
- Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
- PCI compliant (32/33 MHz) at 3.3V
- Differential Signaling
` 622 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
` Bus LVDS I/O
` Lightning Data Transport (LDT) I/O with current driver buffers
` Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O
` Built-in DDR input and output registers
- Proprietary high-performance SelectLink Technology
` High-bandwidth data path
` Double Data Rate (DDR) link
` Web-based HDL generation methodology
• Supported by Xilinx Foundation Series™ and Alliance
Series™ Development Systems
- Integrated VHDL and Verilog design flows
- Compilation of 10M system gates designs
- Internet Team Design (ITD) tool
• SRAM-Based In-System Configuration
- Fast SelectMAP configuration
- Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
- IEEE 1532 support
- Partial reconfiguration
- Unlimited reprogrammability
- Readback capability
• 0.15 m 8-Layer Metal Process with 0.12 m
High-Speed Transistors
• 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V
VCCAUX Auxiliary and VCCO I/O Power Supplies
• IEEE 1149.1 Compatible Boundary-Scan Logic Support

Pinout

Connection Diagram

Specifications

Symbol	Description(1		Units
V_CCINT	Internal supply voltage relative to GND	0.5 to 1.65	V
V_CCAUX	Auxiliary supply voltage relative to GND	0.5 to 4.0	V
V_CCO	Output drivers supply voltage relative to GND	0.5 to 4.0	V
V_BATT	Key memory battery backup supply	0.5 to 4.0	V
V_REF	Input reference voltage	0.5 to VCCO + 0.5	VV
V_IN⁽³⁾	Input voltage relative to GND (user and dedicated I/Os)	0.5 to VCCO + 0.5	V
V_TS	Voltage applied to 3-state output (user and dedicated I/Os)	0.5 to 4.0	V
T_STG	Storage temperature (ambient)	65 to +150	°C
T_SOL	Maximum soldering temperature	+220	°C
T_J	Operating junction temperature (2)	+125	°C

Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website.
3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the
device is not PCI compliant.

Description

The XQ2V6000 includes platform FPGAs developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces.

The XQ2V6000 leading-edge 0.15 m/0.12 m CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 8 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays. As shown in Table 1, the QPro Virtex-II family comprises three members, ranging from 1M to 6M system gates.

XQ2V6000

product image

floor Price/Ceiling Price

Price Break

Month Sales

Rating

Payment Methods

Recent History

Description

Customers Who Bought This Item Also Bought

Line Protection, Backups(300)

Relays(6300)

Switches(5620)

Circuit Protection(3850)

Cable Assemblies(5)

Filters(263)