XCR5032C

The XCR5032C CPLD (Complex Programmable Logic Device) is a member of the CoolRunner ® family of CPLDs from Xilinx. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP design tech- nique, the XCR5032C offers true pin-to-pin speeds of 6 ns, while simultaneously delivering power that is less than  75 µA at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense mplifier methods for implementing product terms (a tech-nique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the pat- ented full CMOS FZP design technique. For 3V applica-tions, Xilinx also offers the high speed XCR3032C CPLD that offers pin-to-pin speeds of 8 ns.

The Xilinx FZP CPLDs utilize the patented XPLA (extended Programmable Logic Array) architecture. The XPLA archi-tecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allo-cation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 6 ns PAL path with five dedicated product terms per output. This PAL path is joined by an dditional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently through- out the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2 ns, regardless of the number of PLA product terms used, which results in orst case tPD's of only 8 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.

The XCR5032C CPLDs are supported by industry standard AE tools (Cadence/OrCAD, Exemplar Logic, Mentor, ynopsys, Synario, Viewlogic, and Synplicity), using text ABEL, VHDL, Verilog) and/or schematic entry. Design ver- fication uses industry standard simulators for functional nd timing simulation. Development is supported on per- onal computer, Sparc, and HP platforms. Device fitting ses Xilinx developed tools including WebFITTER.