XC886

• High-performance XC800 Core
compatible with standard 8051 processor
two clocks per machine cycle architecture (for memory access without wait state)
two data pointers
• On-chip memory
12 Kbytes of Boot ROM
256 bytes of RAM
1.5 Kbytes of XRAM
24/32 Kbytes of Flash; or 24/32 Kbytes of ROM, with additional 4 Kbytes of Flash (includes memory protection strategy)
• I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator)

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (V_IN > V_DDP or V_IN < V_SS) the voltage on VDDP pin with respect to ground (V_SS) must not exceed the values defined by the absolute maximum ratings.

The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state.

Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.

The XC886/888 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and SFRs.

Figure 6 shows the CPU functional blocks.