Features: Complete line of four related Field Programmable Gate Array product families XC3000A, XC3000L, XC3100A, XC3100LIdeal for a wide range of custom VLSI design tasks Replaces TTL, MSI, and other PLD logic Integrates complete sub-systems into a single package Avoids the NRE, time delay, and r...
XC3100L: Features: Complete line of four related Field Programmable Gate Array product families XC3000A, XC3000L, XC3100A, XC3100LIdeal for a wide range of custom VLSI design tasks Replaces TTL, MSI, and oth...
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Complete line of four related Field Programmable Gate Array product families
XC3000A, XC3000L, XC3100A, XC3100L
Ideal for a wide range of custom VLSI design tasks
Replaces TTL, MSI, and other PLD logic
Integrates complete sub-systems into a single package
Avoids the NRE, time delay, and risk of conventional masked gate arrays
High-performance CMOS static memory technology
Guaranteed toggle rates of 70 to 370 MHz, logic delays from 7 to 1.5 ns
System clock speeds over 85 MHz
Low quiescent and active power consumption
Flexible FPGA architecture
Compatible arrays ranging from 1,000 to 7,500 gate complexity
Extensive register, combinatorial, and I/O capabilities
High fan-out signal distribution, low-skew clock nets
Internal 3-state bus capabilities
TTL or CMOS input thresholds
On-chip crystal oscillator amplifier
Unlimited reprogrammability
Easy design iteration
In-system logic changes
Extensive packaging options
Over 20 different packages
Plastic and ceramic surface-mount and pin-grid- array packages
Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options
Ready for volume production
Standard, off-the-shelf product availability
100% factory pre-tested devices
Excellent reliability record
Complete Development System
Schematic capture, automatic place and route
Logic and timing simulation
Interactive design editor for design optimization
Timing calculator
Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
The perimeter of configurable Input/Output Blocks (IOBs) XC3100L provides a programmable interface between the internal logic array and the device package pins. The array of Con-figurable Logic Blocks (CLBs) performs user-specified logic functions. The interconnect resources are programmed to form networks, carrying logic signals among blocks, analo gous to printed circuit board traces connecting MSI/SSI packages.
The XC3100L block logic functions are implemented by programmed look-up tables. Functional options are implemented by pro-gram-controlled multiplexers. Interconnecting networks between blocks are implemented with metal segments joined by program-controlled pass transistors.
These FPGA XC3100L functions are established by a configuration program which is loaded into an internal, distributed array of configuration memory cells. The configuration program is loaded into the device at power-up and may be reloaded on command. The FPGA includes logic and control signals to implement automatic or passive configuration. Program data may be either bit serial or byte parallel. The develop-ment system generates the configuration program bit stream used to configure the device. The memory loading process is independent of the user logic functions.