XC17V01VO8C

The XC17V01VO8C is one member of the XC17V01 series.Multiple PROMs can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All XC17V01VO8C devices are compatible and can be cascaded with other members of the family.If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up/down resistor or keeper circuit.

Features of the XC17V01VO8C are:(1)one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices; (2)simple interface to the FPGA; (3)cascadable for storing longer or multiple bitstreams; (4)programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions ; (5)low-power CMOS floating-gate process; (6)3.3V supply voltage; (7)guaranteed 20 year life data retention; (8)available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20; (9)programming support by leading programmer manufacturers.

The absolute maximum ratings of the XC17V01VO8C can be summarized as:(1)junction temperature:125;(2)storage temperature:-65 to 150;(3)supply voltage relative to GND:-0.5 to 7.0V;(4)supply voltage relative to GND:0.5 to +12.5 V;(5)input voltage relative to GND:0.5 to Vcc+0.5 V;(6)voltage applied to high-Z output:0.5 to Vcc+0.5 V.Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability.Master Serial Mode provides a simple configuration interface. Only one serial data line, two control lines, and one clock line are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK.