XC1700L

Features: • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices• Simple interface to the FPGA; requires only one user I/O pin• Cascadable for storing longer or multiple bitstreams• Programmable reset polarity (activ...

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XC1700L: Features: • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices• Simple interface to the FPGA; requires only one user I/O pin&#...

floor Price/Ceiling Price

Part Number:
XC1700L
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/7

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Product Details

Description



Features:

• One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices
• Simple interface to the FPGA; requires only one user I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
• XC17128E/EL, XC17256E/EL, XC1701 and XC1700L series support fast configuration
• Low-power CMOS Floating Gate process
• XC1700E series are available in 5V and 3.3V versions
• XC1700L series are available in 3.3V only
• Available in compact plastic packages: 8-pin SOIC, 8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-pin PLCC or 44-pin VQFP.
• Programming support by leading programmer manufacturers.
• Design support using the Xilinx Alliance and Foundation series software packages.
• Guaranteed 20 year life data retention



Specifications

Symbol Description
Conditions
Units
VCC

VPP

VIN

VTS

TSTG

TSOL
Supply voltage relative to GND

Supply voltage relative to GND

Input voltage relative to GND

Voltage applied to High-Z output

Storage temperature (ambient)

Maximum soldering temperature (10s @ 1/16 in.)
0.5 to +7.0

0.5 to +12.5

0.5 to VCC +0.5

0.5 to VCC +0.5

65 to +150

+260
V

V

V

V

°C

°C

Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.




Description

The XC1700 family of configuration PROMs provides an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams.

When the  XC1700  FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using theCEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected.

All  XC1700  devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.




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