Features: • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices
• Simple interface to the FPGA; configurable to use a one user I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
• Supports fast configuration
• Low-power CMOS Floating Gate process
• 3.3V supply voltage
• Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20
• Programming support by leading programmer manufacturers.
• Design support using the Xilinx Alliance and Foundation series software packages.
• Dual configuration modes for the XC17V16 and XC17V08
- Serial slow/fast configuration (up to 33 MHz)
- Parallel (up to 264 MHz)
• Guaranteed 20 year life data retentionSpecifications
| Symbol |
Description |
Conditions |
Units |
VCC
VPP
VIN
VTS
TSTG
TSOL |
Supply voltage relative to GND
Supply voltage relative to GND
Input voltage relative to GND
Voltage applied to High-Z output
Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in.) |
0.5 to +7.0
0.5 to +12.5
0.5 to VCC +0.5
0.5 to VCC +0.5
65 to +150
+260 |
V
V
V
V
°C
°C |
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
DescriptionXilinx introduces the high-density XC17V00 family of configuration PROMs which provide an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. Initial devices in the 3.3V family are available in 16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM.
A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The XC17V00 FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM.
When the XC17V00 FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. When the FPGA is in SelectMAP mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. SelectMAP does not utilize a Length Count, so a free-running oscillator may be used. See Figure 3. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected.
All XC17V00 devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.
XC17V00 Data Sheet
