X68C64

Features: • CONCURRENT READ WRITE™ -Dual Plane Architecture -Isolates Read/Write Functions Between Planes -Allows Continuous Execution of Code From One Plane While Writing in the Other Plane• Multiplexed Address/Data Bus -Direct Interface to Popular 8-bit Microcontrollers, e.g., ...

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SeekIC No. : 004547373 Detail

X68C64: Features: • CONCURRENT READ WRITE™ -Dual Plane Architecture -Isolates Read/Write Functions Between Planes -Allows Continuous Execution of Code From One Plane While Writing in the Other P...

floor Price/Ceiling Price

Part Number:
X68C64
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/20

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Product Details

Description



Features:

• CONCURRENT READ WRITE™
   -Dual Plane Architecture
   -Isolates Read/Write Functions Between Planes
   -Allows Continuous Execution of Code From One Plane While Writing in the Other Plane
• Multiplexed Address/Data Bus
   -Direct Interface to Popular 8-bit Microcontrollers, e.g., Motorola M6801/03,M68HC11 Family
• High Performance CMOS
   -Fast Access Time, 120ns
   -Low Power
   -60mA Maximum Active
   -500A Maximum Standby
• Software Data Protection
• Block Protect Register
   -Individually Set Write Lock Out in 1K Blocks
• Toggle Bit Polling
   -Early End of Write Detection
• Page Mode Write
   -Allows up to 32 Bytes to be Written in One Write Cycle
• High Reliability
   -Endurance: 100,000 Write Cycles
   -Data Retention: 100 Years



Pinout

  Connection Diagram


Specifications

Temperature under Bias .................. 65°C to +135°C
Storage Temperature ....................... 65°C to +150°C
Voltage on any Pin with
           Respect to VSS .................................. 1V to +7V
D.C. Output Current ..................................................5mA
Lead Temperature
       (Soldering, 10 seconds) ................................ 300°C



Description

The X68C64 is an 8K x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology.The X68C64 features a Multiplexed Address and Data bus allowing a direct interface to a variety of popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry.

The X68C64 is internally configured as two independent 4K x 8 memory arrays. This feature provides the ability to perform nonvolatile memory updates in one array and continue operation out of code stored in the other array;effectively eliminating the need for an auxiliary memory device for code storage.

To write to the X68C64, a three-byte command sequence must precede the byte(s) being written. The X68C64 also provides a second generation software data protection scheme called Block Protect. Block Protect can provide write lockout of the entire device or selected 1K blocks. There are eight 1K x 8 blocks that can be write protected individually in any combination required by the user. Block Protect, in addition to Write Control input, allows the different segments of the memory to have varying degrees of alterability in normal system operation.




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