WS-128K8

The white technology model WS-128K8 is a CMOS SRAM housed in a hermetically sealed ceramic32 pin package. Featuring JEDEC standard pinouts, the device provides 128K bytes of read/write low power memory. The WS-128K8 is well suited for battery backed operation and will retain data at voltages as low as 2.0 volts. Designed for use in demanding applications, the memory packaging and construction is well suited for military and severe industrial application. screening and burn in are to military standards.

The advanced 128K*8 SRAM is constructed using co-fired ceramic packaging and high density COMOS memory. The module also features internal power supply bypass capacitors to enhance performance. Inputs and outputs are TTL compatible. The logic levels and drive capabilities permit the memory to interface with most digital logic systems. Since the WS-128K8 is all CMOS, low power operation for standby applications such as battery backed systems is straightforward. The memory features low power consumption. In typical systems where multiple modules are operating using chip select to activate each device, the overall current requirement is only slightly above that for one unit. Those units not selected require only standby current. Since the WS-128K8 is a fully static memory,refreshing is not needed. The memory read and write cycles are compatible with virtually all microprocessors. The maximum read and write acess time from address change or chip enable is as specified. The rugged ceramic package features a welded metal cover and co-fired construction to assure maximunm integrity and hermetic seal. The package is desighed and rated to meet military specifications.

The memory has seventeen address lines, Ao through A16. These lines combine to select a specific bytes from the memory array of 128K(131,072bytes). The data input and output of WS-128K8 share a common read/write data bus I/O0 through I/O7. Additional control lines with inverse sense logic are CS(chip select), WE(write enable), and OE(output enable). When asserted low, the chip enable line selects the memory and permits response to the write enable and line selects the memory and permits response to the write enable and output enable lines. When the chip enable line is high, the memory is deactivated and current drain is sharply reduced. The write enable line is asserted low. To present the data to the I/O bus, the output enable line is set to high impedance and no data is presented to the I/O bus. The timing diagrams of figures 4 and 5 illustrate the preferred timing sequence and timing specifications for the memory. The output enable line is high during write cycles while the write enable line is high during read cycles. The memory of WS-128K8 is designed to operate and interface with TTL and CMOS logic levels. The memory will also retain data at lower levels of Vcc.