Features: • Two 10-bit resolution ADCs• 40MSPS conversion rate• Simultaneous sampling differential input PGAs with 0 to 18dB gain• Programmable clock / output data formats − 10-bit multiplexed or 20-bit wide output − Input clock at sample rate or twice sample ra...
WM2124: Features: • Two 10-bit resolution ADCs• 40MSPS conversion rate• Simultaneous sampling differential input PGAs with 0 to 18dB gain• Programmable clock / output data formats ...
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CONDITION |
MIN |
MAX |
Digital supply voltage, DVDD to DVSS |
-0.5V |
+3.6V |
Digital output driver supply voltage, DRVDD to DRVSS |
-0.5V |
+3.6V |
Analogue supply voltage, AVDD to AVSS |
-0.5V |
+3.6V |
Maximum ground difference between AVSS, DVSS and DRVSS |
-0.5V |
+0.5V |
Voltage range digital inputs |
DVSS 0.5V |
DVDD + 0.5V |
Voltage range analogue inputs (includes CLK pin) |
AVSS - 0.5V |
AVDD + 0.5V |
Operating temperature range, TA |
-45°C |
+85°C |
Storage temperature |
-65°C |
+150°C |
Lead temperature (1.6mm from case for 10 seconds) |
|
+300°C |
The WM2124 is a dual channel 10-bit 40MSPS ADC which consumes only 275mW from a single 3.3V supply. The device is optimised for communications applications that require close matching between channels and a wide input bandwidth.
Input signals of the WM2124 are differential for improved noise performance. Both A and B input channels are sampled simultaneously and are processed through matched signal paths of programmable gain amplifier (PGA) and 10-bit multistage pipeline ADC. A number of different input clock / output data formats are supported including 20-bits wide at the sampling rate or 10-bits wide at twice the sampling rate,with additional clock outputs supplied by the device to latch the output data.
System design and power requirements are further simplified by the provision of an on-chip precision voltage reference. Alternatively, external references can be used if higher precision references are required.
The WM2124 is programmed via a 3-wire serial interface which allows control of PGA gain setting (0 to 18dB range),clock / output data formatting, powerdown control and binary or two's complement number formatting.