WED2ZLRSP01S

Features:

· Fast clock speed: 166, 150, 133, and 100MHz
· Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
· Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
· Single +2.5V ± 5% power supply (V_CC)
· Snooze Mode for reduced-standby power
· Individual Byte Write control
· Clock-controlled and registered addresses, data I/Os and control signals
· Burst control (interleaved or linear burst)
· Packaging:
· 209-bump BGA package
· Low capacitive bus loading


Specifications

Voltage on Vdd Supply Relative to VSS	-0.3V to +3.6V
VIN (DQx)	-0.3V to +3.6V
VIN (Inputs)	-0.3V to +3.6V
Storage Temperature (BGA)	-55 to +125
Short Circuit Output Current	100mA

*Stress greater than those listed under "Absolute Maximum Ratings": may cause permanent damage to 
  the device. This is a stress rating only and functional operation of the device at these or any other
  conditions greater than those indicated in the operational sections of this specifi cation is not implied. Exposure
  to absolute maximum rating condtions for extended periods may affect reliability.


Description

The WED2ZLRSP01S, Dual Independent Array, NBLSSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC's 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256K x 32.

All Synchronous inputs of the WED2ZLRSP01S pass through registers controlled by a positive edge triggered, single clock input per array. The NBL or No Bus Latency Memory provides 100% bus utilizaton, with no loss of cycles caused by change in modal operation (Write to Read/Read to Write). All inputs except for Asynchronous Output Enable and Burst Mode control are synchronized on the positive or rising edge of Clock. Burst order control must be tied either HIGH or LOW, Write cycles are internally self-timed, and writes are initiated on the rising edge of clock. This feature of the WED2ZLRSP01S eliminates the need for complex off-chip write pulse generation and proved increased timing fl exibility for incoming signals.