WED2ZL64512S

*Stress greater than those listed under "Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.

The WED2ZL64512S SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WED2ZL64512S's 32Mb Sync SRAM integrate two 512K x 32 SRAMs into a single BGA package to provide 512K x 64 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CK). The NBL or No Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable a e synchronized to input clock. Output Enable controls the outputs at any given time and to Asynchronous Input. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature of WED2ZL64512S eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals.