WED2EG472512V-D2

Features: · 4x512Kx72 Synchronous, Synchronous Burst· Pipeline Architecture; Dual Cycle Deselect· Linear and Sequential Burst Support via MODE pin· Clock Controlled Registered Module Enable (EM)· Clock Controlled Registered Bank Enables (E1, E2, E3, E4)· Clock Controlled Byte Write Mode Enable (BW...

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SeekIC No. : 004545548 Detail

WED2EG472512V-D2: Features: · 4x512Kx72 Synchronous, Synchronous Burst· Pipeline Architecture; Dual Cycle Deselect· Linear and Sequential Burst Support via MODE pin· Clock Controlled Registered Module Enable (EM)· Cl...

floor Price/Ceiling Price

Part Number:
WED2EG472512V-D2
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/7/26

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Product Details

Description



Features:

· 4x512Kx72 Synchronous, Synchronous Burst
· Pipeline Architecture; Dual Cycle Deselect
· Linear and Sequential Burst Support via MODE pin
· Clock Controlled Registered Module Enable (EM)
· Clock Controlled Registered Bank Enables (E1, E2, E3, E4)
· Clock Controlled Byte Write Mode Enable (BWE)
· Clock Controlled Byte Write Enables (BW1 - BW8)
· Clock Controlled Registered Address
· Clock Controlled Registered Global Write (GW)
· Asynchronous Output Enable (G)
· Internally Self-Timed Write
· Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4)
· Gold Lead Finish
· 3.3V ± 10% Operation
· Frequency(s): 200, 166, 150 and 133MHz
· Access Speed(s): tKHQV = 3.0, 3.5, 3.7 and 4.0ns
· Common Data I/O
· High Capacitance (30pF) Drive, at Rated Access Speed
· Single Total Array Clock
· Multiple Vcc and Gnd for Improved Noise Immunity



Pinout

  Connection Diagram


Specifications

Voltage on Vcc Relative to Vss

Vin

Storage Temperature

Operating Temperature (Commercial)

Operating Temperature (Industrial)

Short Circuit Output Current
-0.3V to +4.6V

-0.3V to Vcc +0.5V

-55°C to + 125°C

0°C to +70°C

-40°C to +85°C

100mA

*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.




Description

The WED2EG472512V-D2 is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72. The Module contains sixteeen (16) Synchronous Burst RAM devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The Module Architecture is defined as a Sync/SyncBurst, Pipeline, with support for either linear or sequential burst. This Module provides high performance, 3-1-1-1 accesses when used in Burst Mode.

Synchronous Only operations of the WED2EG472512V-D2 are performed via strapping ADSC Low, and ADSP/ADV High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes.

Synchronous/Synchronous Burst operations of the WED2EG472512V-D2 are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output Enable. This Module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as Quad Words in both Read and Write Operations.




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