WED2DL36513V

*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The WEDC SyncBurst - SRAM family of the WED2DL36513V employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process. WEDC's 16Mb SyncBurst SRAMs integrate two 512K x 18 SRAMs into a single BGA package to provide 512K x 36 configuration. All synchronous inputs pass through registers controlled by a positive - edge-triggered single-clock input (CLK).

The synchronous inputs of the WED2DL36513V include all addresses, all data inputs, active LOW chip enable (CE), burst control inputs (ADSC, ADSP, ADV), byte write enables (BW0-3) and global write (GW). Asynchronous inputs include the output enable (OE), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. Write Cycles can be from one to four bytes wide, as  ontrolled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP) or address status controller (ADSC) inputs. Subsequent burst addresses of the WED2DL36513V can be internally generated as controlled by the burst advance input (ADV).