Description
Features:
Architecture
• Fully 16/32-bit RISC architecture
• Little/Big-Endian mode supported
• Efficient and powerful ARM7TDMI core
• Cost-effective JTAG-based debug solution
External Bus Interface
• 8/16-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os
• Support for SDRAM
• Programmable access cycle (0-7 wait cycle)
• Four-word depth write buffer for SDRAM write data
• Cost-effective memory-to-peripheral DMA interface
Instruction and Data Cache
• Two-way, set-associative, 4K-byte I-cache and 4K-byte D-cache
• Support for LRU (Least Recently Used) protocol
• Cache can be configured as internal SRAM
• Support cache lock function
Ethernet MAC Controller
• DMA engine with burst mode
• MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)
• Data alignment logic
• Endian translation
• 100/10 Mbit per second operation
• Full compliance with IEEE standard 802.3
• RMII interface only
• Station Management Signaling
• On-chip CAM (up to 16 destination addresses)
• Full-duplex mode with PAUSE feature
• Long/short packet modes
• PAD generation
DMA Controller
• 2-channel general DMA for memory-to-memory data transfers without CPU intervention
• Initialed by a software or external DMA request
• Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers
• 4-data burst mode
UART
• Four UART (serial I/O) blocks with interrupt-based operation
• Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive
• Programmable baud rates
• 1, ½ or 2 stop bits
• Odd or even parity
• Break generation and detection
• Parity, overrun and framing error detection
• X16 clock mode
• UART1 supports Bluetooth, and UART2 supports IrDA1.0 SIR
Timers
• Two programmable 24-bit timers with 8-bit pre-scaler
• One programmable 20 bit with selectable additional 8-bit prescaler watchdog timer
• One-shot mode, periodical mode or toggle mode operation
Programmable I/Os
• 31 programmable I/O ports
• Pins individually configurable to input, output or I/O mode for dedicated signals
• I/O ports are configurable for multiple functions
Advanced Interrupt Controller
• 24 interrupt sources, including 4 external interrupt sources
• Programmable normal or fast interrupt mode (IRQ, FIQ)
• Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources
• Programmable as either low-active or high-active for 4 external interrupt sources
• Priority methodology is encoded to allow for interrupt daisy-chaining
• Automatically mask out the lower priority interrupt during interrupt nesting
USB Host Controller
• USB 1.1 compliant
• Compatible with Open HCI 1.0 specification
• Supports low-speed and full speed devices
• Build-in DMA for real time data transfer
• Two on-chip USB transceivers with one optionally shared with USB device controller
USB Device Controller
• USB 1.1 compliant
• Support four USB endpoints including one control endpoint and 3 configurable endpoints for rich
USB functions
Two PLLs
• The external clock can be multiplied by on-chip PLL to provide high frequency system clock
• The input frequency range is 3-30MHz; 15MHz is preferred.
• One PLL for both CPU and USB host/device controller
• One PLL for audio I²S 12.288/16.934MHz clock source
• Programmable clock frequency
4-Channel PWM
• Four 16-bit timers with PWM
• Two 8-bit pre-scalers & Two 4-bit dividers
• Programmable duty control of output waveform (PWM)
• Auto reload mode or one-shot pulse mode
• Dead-zone generator
I2C Master
• 2-channel I2C
• Compatible with Philips I2C standard, support master mode only
• Support multi master operation
• Clock stretching and wait state generation
• Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer
• Software programmable acknowledge bit
• Arbitration lost interrupt, with automatic transfer cancellation
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus busy detection
• Supports 7 bit addressing mode
• Software mode I2C
Universal Serial Interface (USI)
• 1-channel USI
• Support USI (Microwire/SPI) master mode
• Full duplex synchronous serial data transfer
• Variable length of transfer word up to 32 bits
• Provide burst mode operation, transmit/receive can be executed up to four times in one transfer
• MSB or LSB first data transfer
• Rx and Tx on both rising or falling edge of serial clock independently
• Two slave/device select lines
• Fully static synchronous design with one clock domain
2-Channel AC97/I²S Audio Codec Host Interface
• AHB master port and an AHB slave port are offered in audio controller.
• Always 8-beat incrementing burst
• Always bus lock when 8-beat incrementing burst
• When reach middle and end address of destination address, a DMA_IRQ is requested to CPU
automatically
KeyPad Scan Interface
• Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4x8 array without auxiliary
component
• Programmable debounce time
• One or two keys scan with interrupt and three keys reset function.
• Wakeup CPU from IDEL/Power Down mode
PS2 Host Interface
• APB slave consisted of PS2 protocol.
• Connect IBM keyboard or bar-code reader through PS2 interface.
• Provide hardware scan code to ASCII translation
Power management
• Programmable clock enables for individual peripheral
• IDLE mode to halt ARM core and keep peripheral working
• Power-Down mode to stop all clocks included external crystal oscillator.
• Exit IDLE by all interrupts
Exit Power-Down by keypad,USB device and external interrupts
Operation Voltage Range
• 3.0 ~ 3.6 V for IO buffer
• 1.62 ~ 1.98 V for core logic
Operation Temperature Range
• TBD
Operating Frequency
• Up to 80 MHz
Package Type
• 128-pin LQFP
W90N745CD Data Sheet
